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TAS5110ADADR Datasheet(PDF) 10 Page - Texas Instruments |
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TAS5110ADADR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 17 page TAS5110A SLES079A – APRIL 2003 – REVISED MAY 2003 www.ti.com 10 RECOMMENDED OPERATING CONDITIONS (maximum output power = 50 W (RMS), TJ = 25°C) Thermal Data(1) MIN NOM MAX UNIT TJ(SD) Shutdownjunction temperature 150 °C TJ(W) Warning junction temperature 125 °C TC Operatingtemperature Commercial 0 25 70 °C R θJC(2) Thermalresistancejunction-to-case 2 oz trace and copper pad without solder 1.6 °C/W R θJA(2) Thermalresistancejunction-to-ambient 2 oz. trace and copper pad without solder 44.3 °C/W (1) One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat dissipatingabilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and solderable), deep downset pad. See Appendix A of the PowerPAD Thermally Enhanced Package technical brief, TI literature number SLMA002. (2) For the DAD package. RL = 6 Ω to 8 Ω MIN NOM MAX UNIT Digital DVDD to DVSS 3 3.3 3.6 V PVDDA2 to PVSS 16.5 22 26.5 Supply voltage Regulator PVDDB2 to PVSS 16.5 22 26.5 V yg Regulator PVDDA2 to PVSS(1) 10.5 16.5 V PVDDB2 to PVSS(1) 10.5 16.5 (1) ConnectLDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition, the H-bridgeforwardon-stateresistanceisincreased. This increases internal power dissipation. Maximum output power may need to be reduced to meet thermal conditions. Maximum Available Power at Common Load Impedances for the DAD Package Unclipped (0 dB) Level(1) LOAD IMPEDANCE PVDAA1/PVDDB1 APPROXIMATE MAXIMUM THD+N AT MAXIMUM POWER LOAD IMPEDANCE ( Ω) PVDAA1/PVDDB1 (VDC) APPROXIMATE MAXIMUM OUTPUT POWER (W) THD+N AT MAXIMUM POWER AND 1-kHz INPUT(2) 6 27 50 < 10% 6 27 43 < 0.09% 8 27 34 < 0.09% (1) Dependent on board design and component selection (2) Test conditions are described in the Thermal Methodology for the 32-Pin DAD Package 50 W, 6- Ω Test. STATIC DIGITAL SPECIFICATIONS RESET, PWDN, PWM_AP, PWM_AM, PWM_BP, PWM_BM, TJ = 25°C, DVDD = 3.3 V PARAMETERS MIN MAX UNIT VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V Input leakage current –10 10 µA ERR0, ERR1, SHUTDOWN, (Open Drain With Internal Pullup Resistor) TJ = 25°C, DVDD = 3.3 V) PARAMETERS MIN MAX UNIT Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD 15 k Ω VOL Low-level output voltage (IO = 4 mA) 0.4 V |
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