RP102x

NO.EA-141-160705

3

PIN CONFIGURATIONS

Mark Side

Bump Side

2

1

A

B

B

A

2

1

Top View

6

5

4

1

2

3

Bottom View

4

5

6

3

2

1

1

1

2

3

4

5

(mark side)

PIN DESCRIPTION

Pin No

Symbol

Pin Description

A1

Input Pin

A2

Output Pin

B1

CE

Chip Enable Pin ("H" Active)

B2

GND

Ground Pin

Pin No

Symbol

Pin Description

1

2

3

GND

Ground Pin

4

CE

Chip Enable Pin ("H" Active)

5

6



1) Tab is GND level. (They are connected to the reverse side of this IC.)

The tab is better to be connected to the GND, but leaving it open is also acceptable.

2) No.1 pin and No.2 pin, No.5 pin and No.6 pin of DFN(PLP)1820-6 package must be wired when it is

mounted on board.

Pin No

Symbol

Pin Description

1

Input Pin

2

GND

Ground Pin

3

CE

Chip Enable Pin ("H" Active)

4

NC

No Connection

5

Output Pin