PC-414

®®

DATEL, Inc., Mansfield, MA 02048 (USA)

• Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 • Email: sales@datel.com • Internet: www.datel.com

SPECIFICATIONS, CONTINUED

(Typical @ +25°C, dynamic conditions, unless noted)

A/D MEMORY

Architecture

First-In, First-Out (FIFO)

Memory Capacity

1024, 4096, or 16,384 A/D

samples. 64 K on request.

Programmable Interval

Timer Type

82C54

Functions

1. A/D sample count reached

2. A/D start rate (16 bit divisor)

3. SSH sample counter (414A)

Pacer Sample Counter

3 to 65,536 samples. Drives

the Acquire flag/interrupt

gate for A/D start pulses.

82C54 Clock Source

Internal 8 MHz crystal clock

Scan Trigger Clock

125, 250, or 500 KHz

Analog Trigger Input Range

[Note 5]

±10 V (not avail. 414D)

Analog Trigger Response

2 µs to set status flag

Analog Trigger Hysteresis

40 mV

Number of Channels

One

Function

1. General purpose analog

(user-selectable)

output

[Note 5]

2. Threshold comparator for

A/D trigger

Resolution

12 bits

Output Voltage Range

0 to +10 V, ±5 V and ±10 V

(user-selectable)

at 5 mA max.

Linearity

±0.05% of FSR

Settling Time

(10 V step)

5 microseconds to 0.05%

Input Coding

(user-selectable)

Same as A/D section

Architecture

I/O mapped, pluggable to

IBM-PC/AT, and compatibles.

Decodes eight 16-bit I/O

registers.

I/O Mapping

Decodes I/O address lines

A9 - A0

Data Transfer

I/O transfer or host DMA,

software selectable

Data Bus

16 bits

Direct Memory Access

1 channel, selectable on

channels 5, 6, or 7, set by

software

DMA Request Conditions

FIFO full, half full, not empty,

(software selectable)

scan acquire flag (sample

count reached)

Control/Status Functions

Board reset, FIFO flags,

interrupt select and status,

DMA select and status, trigger

source, timer control and

period, sample count load,

parallel outport enable, A/D

enable, MUX auto-sequence

Number of Interrupts

1 interrupt, software

(software selectable)

selectable on level 7, 9 thru

11, or 15.

Bus Interrupt Sources

Scan acquire flag (sample

count), FIFO full or half full,

DMA terminal count from bus.

Outport Type

16 data output lines, TTL

levels from A/D FIFO.

Includes handshake signals

and FIFO flags. The outport

does not provide addressing.

Operating Modes

Asynchoronous master to

external slave receiver. 4

modes are included, offering

internal/external clocking (to

10 MHz), synchronous/

asynchronous handshaking.

Sequencing is compatible

Parallel Port Loading

24 mA out, 1.6 mA in. The

data outputs may be tri-stated

for shared bus connection.

Parallel Port Connector

2-row 26-pin header type

mounted on board interior.

0.100” pin spacing suitable

for flat cable. Pinout is

and existing 414 format.

Port Data Rate

4 MHz max. Data may be

transferred up to 10 MHz

with external clocking.

Connector

Dual row, 26-pin header

mounted on board interior.

Uses 0.100” pin spacing

suitable for flat cable.

Includes +5 Vdc and digital

ground connections.

Configuration

8 digital outputs, 8 digital

inputs (unlatched)

Levels

Buffered, TTL levels.

10 output loads.

Outport Settling Time

50 ns max. after write operation

Analog Section Modularity

The MUX-S/H-A/D module is

socketed for function

interchange.

Analog Section Adjustments

Offset and gain per channel

for SSH on PC-414F, G, H,

K, M, N, and P. A single

offset and gain pot is

provided on PC-414B, D,

and E. Recommended

recalibration interval is 90

days in stable conditions.

Analog Input Connectors

Four SMA miniature coaxial,

mounted on rear slot. [Note 8]

TRIGGER CONTROL

PARALLEL DATA PORT

DIGITAL I/O PORT

MISCELLANEOUS

ANALOG OUTPUT

ISA BUS INTERFACE

84