PC-414

®®

DATEL, Inc., Mansfield, MA 02048 (USA)

• Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 • Email: sales@datel.com • Internet: www.datel.com

I/O Register Mapping

The base address may be selected anywhere up to 3F0h on

16-byte boundaries.

I/O Address

(hex)

Direction

Description

Base + 0

Write

Command Register

Base + 0

Read

Status Register

Base + 2

Write

Channel Address/Digital

Output [Note 12]

Base + 2

Read

Digital Input Register

[Note 12]

Base + 4

Write

D/A Data Register

Base + 6

Write

FIFO Reset Register

Base + 6

Read

FIFO A/D Data Register

Base +8

Read/Write

Counter #0 (82C54)

Base + 0Ah

Read/Write

Counter #1 (82C54)

Base + 0Ch

Read/Write

Counter #2 (82C54)

Base + 0Eh

Read/Write

Control Register (82C54)

Transfer Speeds

ISA bus transfer rates are host-dependent and should be

determined by testing. For example, a Compaq computer

achieved 800 nanoseconds instantaneous sample-to-sample

timing to base memory using the REP INSW instruction. A

faster CPU will not increase the ISA bus speed. To optimize

throughput, disable all possible interrupts. For higher speed

continuous (non-stop) A/D sampling, consider using a parallel

port.

Figure 4. PC-414 Timing DIagram

Internal or external trigger rate

TRIGGER

A/D

START

CONVERT

END OF

SCAN*

(Internal

(Signal)

ACQUIRE

FLAG

Maskable Interrupt

and Status

01

2

3

Fixed or sequential channel addressing up to

64k samples per trigger

SSH (Internal)

[BASE + 0 bit 2 = 1]

(414A only)

HOLD

SAMPLE

Internal or external start rate

Figure 3. Array Preprocessing

Analog

Inputs

Binary A/D Data

Parallel

Port

DSP Arrays

PC/AT Bus

Graphics

Display

Mass Storage

PC-414

MUX

A/D

FIFO

MEM

Array

Processor

Board

CPU

Disk

Controller

Display

Controller

See model PC-414COM

using a DSP COMM

port interface.

FIFO Data Format

A/D data is delivered as a stream from the FIFO memory. For

multichannel inputs, this means that data is multiplexed. For

example, for 4-channel inputs, the output channel sequence is

0, 1, 2, 3, 0, 1, . . . Some applications may need this data de-

multiplexed by software so that each channel’s data is placed

in its own separate buffer.

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