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ISL29034 Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL29034 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 14 page ISL29034 7 FN8370.2 August 19, 2016 Submit Document Feedback Ambient Light and IR Sensing There are four operational modes in ISL29034: Programmable ALS once with auto power-down, programmable IR sensing once with auto power-down, programmable continuous ALS sensing and programmable continuous IR sensing. These four modes can be programmed in series to fulfill the application needs. The detailed program configuration is listed in “Command-I Register (Address: 0x00)” on page 9. When the part is programmed for ambient light sensing, the ambient light with wavelength within the “Ambient Light Sensing” spectral response curve in Figure 15 is converted into current. With ADC, the current is converted to an unsigned n-bit (up to 16 bits) digital output. When the part is programmed for infrared (IR) sensing, the IR light with wavelength within the “IR Sensing” spectral response curve in Figure 15 is converted into current. With ADC, the current is converted to an unsigned n-bit (up to 16 bits) digital output. Serial Interface The ISL29034 supports the Inter-Integrated Circuit (I2C) bus data transmission protocol. The I2C bus is a two-wire serial bidirectional interface consisting of SCL (Clock) and SDA (Data). Both the wires are connected to the device supply via pull-up resistors. The I2C protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The transmitting device pulls down the SDA line to transmit a “0” and releases it to transmit a “1”. The master always initiates the data transfer, only when the bus is not busy, and provides the clock for both transmit and receive operations. The ISL29034 operates as a slave device in all applications. The serial communication over the I2C interface is conducted by sending the Most Significant Bit (MSB) of each byte of data first. Start Condition During data transfer, the SDA line must remain stable while the SCL line is HIGH. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (refer to Figure 12 on page 8). The ISL29034 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (refer to Figure 12). A START condition is ignored during the power-up sequence. Stop Condition All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (refer to Figure 12). A STOP condition at the end of a read/write operation places the device in its standby mode. If a stop is issued in the middle of a Data byte, or before 1 full Data byte + ACK is sent, then the serial communication of the ISL29034 resets itself without performing the read/write. The contents of the array are not affected. Acknowledge An Acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device releases the SDA bus after transmitting 8 bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (refer to Figure 12). The ISL29034 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again, after successful receipt of an Address Byte. The ISL29034 also responds with an ACK after receiving a Data byte of a write operation. The master must respond with an ACK after receiving a Data byte of a read operation. Device Addressing Following a START condition, the master must output a Device Address byte. The 7 MSBs of the Device Address byte are known as the device identifier. The device identifier bits of the ISL29034 are internally hard-wired as “1000100”. The LSB of the Device Address byte is defined as a Read or Write (R/W) bit. When this R/W bit is a “1”, a read operation is selected and when “0”, a write operation is selected (refer to Figure 10). The master generates a START condition followed by Device Address byte 1000100x (x as R/W) and the ISL29034 compares it with the internal device identifier. Upon a correct comparison, the device outputs an acknowledge (LOW) on the SDA line (refer to Figure 12). Write Operation BYTE WRITE In a byte write operation, the ISL29034 requires the Device Address byte, Register Address byte, and the Data byte. The master starts the communication with a START condition. Upon receipt of the Device Address byte, Register Address byte and the Data byte, the ISL29034 responds with an Acknowledge (ACK). Following the ISL29034 data acknowledge response, the master terminates the transfer by generating a STOP condition. The ISL29034 then begins an internal write cycle of the data to the volatile memory. During the internal write cycle, the device inputs are disabled and the SDA line is in a high impedance state, so the device will not respond to any requests from the master (refer to Figure 11). BURST WRITE The ISL29034 has a burst write operation, which allows the master to write multiple consecutive bytes from a specific address location. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first Data byte is transferred, the master can write to the whole register array. After the receipt of each byte, the ISL29034 responds with an acknowledge, and the address is internally incremented by one. The address pointer remains at the last address byte written. When the counter reaches the end of the register address list, it “rolls over” and goes back to the first Register Address. DEV ICE ADD RESS BYT E REG IS T ER ADD RESS B YT E D A T A BY T E 1 0 0 0 1 0 0 R/W A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 10. DEVICE ADDRESS, REGISTER ADDRESS AND DATA BYTE |
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