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74LVCH162244APAG8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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74LVCH162244APAG8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 6 page INDUSTRIALTEMPERATURERANGE IDT74LVCH162244A 3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS 1 AUGUST 2015 INDUSTRIAL TEMPERATURE RANGE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. © 2015 Integrated Device Technology, Inc. DSC-4727/6 FEATURES: • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) •VCC = 3.3V ± 0.3V, Normal Range •VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4 μμμμμ W typ. static) • All inputs, outputs, and I/O are 5V tolerant • Available in TSSOP package FUNCTIONAL BLOCK DIAGRAM APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DRIVE FEATURES: • Balanced Output Drivers: ±12mA • Full internal series termination IDT74LVCH162244A DESCRIPTION: The LVCH162244A 16-bit buffer/driver is built using advanced dual metal CMOS technology. The LVCH162244A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The devicecanbeusedasfour4-bitbuffers,two8-bitbuffers,orone16-bitbuffer. Thisdeviceprovidestrueoutputsandsymmetricalactive-lowoutput-enable (OE) inputs. All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH162244A has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been developed to drive ±12mA at the designated threshold levels. The LVCH162244A has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, AND BUS-HOLD 1 A1 1 A2 1 A3 1 A4 1 Y1 1 OE 1 Y2 1 Y3 1 Y4 2 A1 2 A2 2 A3 2 A4 2 Y1 2 OE 2 Y2 2 Y3 2 Y4 3 A1 3 A2 3 A3 3 A4 3 Y1 3 OE 3 Y2 3 Y3 3 Y4 4 A1 4 A2 4 A3 4 A4 4 Y1 4 OE 4 Y2 4 Y3 4 Y4 1 47 46 44 43 48 41 40 38 37 2 3 5 6 8 9 11 12 25 36 35 33 32 24 30 29 27 26 13 14 16 17 19 20 22 23 |
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