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S-77101AXX-T8T1U4 Datasheet(PDF) 10 Page - Seiko Instruments Inc |
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S-77101AXX-T8T1U4 Datasheet(HTML) 10 Page - Seiko Instruments Inc |
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10 / 40 page  POWER SEQUENCER S-77100/77101 Series Rev.1.0_01 10 1. 2 S-77101A (Reverse type, with OFF _______ pin), S-77101B (Forward type, with OFF _______ pin) The S-77101 Series has enable outputs of 3 channels (the ENBL_A pin, the ENBL_B pin and the ENBL_C pin) and the OFF _______ pin. The order of the off-sequence operation is different in reverse type and forward type. 1. 2. 1 Sequence operation outline (1) On-sequence operation After the ON pin changes from "L" to "H", the external capacitor (CDLY) charge operation is started, and the discharge operation is performed when CDLY is fully charged. The period during which this is repeated n times is the delay time (tDLY), and the ENBL_A pin changes to "H". Similarly, each time tDLY elapses, the ENBL_B pin and the ENBL_C pin change to "H" in turn. The period from when the ON pin changes from "L" to "H" to when the ENBL_C pin changes to "H" is called "on-sequence period". (2) Off-sequence operation After the OFF _______ pin changes from "H" to "L", CDLY charge operation is started, and the discharge operation is performed when CDLY is fully charged. The period during which this is repeated n times is tDLY, and the ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to "L" in turn in S-77101A. The ENBL_A pin, the ENBL_B pin and the ENBL_C pin change to "L" in turn in S-77101B. The period from when the OFF _______ pin changes from "H" to "L" to when the ENBL_A pin in S-77101A or the ENBL_C pin in S-77101B changes to "L" is called "off-sequence period". Do not change the ON pin and the OFF _______ pin during on-sequence period and off-sequence period in order to perform the sequence operation normally. The number of times of CDLY charge and discharge which determines tDLY can be selected from 2 times / 4 times / 8 times / 16 times as the option. CDLY charge operation and the discharge operation to generate the tDLY are performed by the constant current circuit. Refer to " Relation between Delay Time and External Capacitor" for the relation of CDLY and tDLY. In addition, the period from when the ENBL_A pin, the ENBL_B pin and the ENBL_C pin all change to "H" to when the off-sequence operation starts is called "power-good period", and the period from when the ENBL_A pin, the ENBL_B pin and the ENBL_C pin all change to "L" to when the on-sequence operation starts is called "off period". The sequence operation is not affected even if the ON pin changes from "H" to "L" during power-good period or the OFF _______ pin changes from "L" to "H" during off period. Refer to Figure 8 for the peripheral circuit connection example. Timing charts are shown in Figure 9 and Figure 10 for S-77101A and S-77101B, respectively. IN EN OUT IN EN OUT IN EN OUT S-77101 Series 0.1 F VDD VSS OFF ON CDLY ENBL_A ENBL_B ENBL_C 5 V AUX DC-DC LDO DC-DC LDO DC-DC LDO DC-DC LDO IN OUT 3.3 V System I/O(1) I/O(2) LOGIC 2.5 V 1.8 V 1.5 V Remark The ENBL_x pin is CMOS output. Figure 8 Peripheral Circuit Connection Example (S-77101A: Reverse Type, with OFF _______ pin, S-77101B: Forward Type, with OFF _______ pin) Caution 1. The input should be performed after the power supply voltage applied to the S-77101 Series becomes stable condition. 2. The above connection diagram does not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. |
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