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SL28PCIE14 Datasheet(PDF) 8 Page - Silicon Laboratories |
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SL28PCIE14 Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 13 page SL28PCIe14 DOC#: SP-AP-0014 (Rev. 0.2) Page 8 of 13 AC Electrical Specifications Parameter Description Condition Min. Max. Unit Crystal LACC Long-term Accuracy Measured at VDD/2 differential – 250 ppm Clock Input TDC CLKIN Duty Cycle Measured at VDD/2 47 53 % TR/TF CLKIN Rise and Fall Times Measured between 0.2VDD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter (Sythesizer) Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V VIL Input Low Voltage XIN / CLKIN pin – 0.8 V IIH Input HighCurrent XIN / CLKIN pin, VIN = VDD – 35 uA IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN <0.8 –35 – uA SRC at 0.7V TDC Duty Cycle Measured at 0V differential 45 55 % RMSGEN1 Output PCIe* Gen1 REFCLK phase jitter BER = 1E-12 (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz) 0108 ps RMSGEN2 Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 03.0 ps RMSGEN2 Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 03.1 ps RMSGEN3 Output phase jitter impact – PCIe* Gen3 Includes PLL BW 2 - 4 MHz, CDR = 10MHz) 01.0 ps TCCJ Cycle to Cycle Jitter Measured at 0V differential – 85 ps TCCJ Additive Cycle to Cycle Jitter In buffer mode. Measured at 0V differential –50 ps LACC Long-term Accuracy Measured at 0V differential – 100 ppm TR / TF Rising/Falling Slew rate Measured differentially from ±150 mV 2.5 8 V/ns VOX Crossing Point Voltage at 0.7V Swing 300 550 mV ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up – 1.8 ms TSS Stopclock Set-up Time 10.0 – ns |
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