3.1 Device Startup

Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow

the states of inputs.

3.2 Undervoltage Lockout

Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its

specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or

Figure 3.1. Device Behavior during Normal Operation

3.3 Layout Recommendations

digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large

high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.6 Insulation and Safety-Related

Specifications on page 19 and Table 4.8 IEC 60747-5-5 Insulation Characteristics for Si86xxxx 1 on page 20 detail the working volt-

age and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA

5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-

system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.

3.3.1 Supply Bypass

as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series

with the inputs and outputs if the system is excessively noisy.

3.3.2 Output Pin Termination

The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-

chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will

be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.

3.4 Fail-Safe Operating Mode

Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)

can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si86xx Logic Operation on page 4 and

1. Ordering Guide for more information.

Si8630/31/35 Data Sheet

Device Operation

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