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Si8261ACC-C-IS Datasheet(PDF) 5 Page - Silicon Laboratories |
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Si8261ACC-C-IS Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 40 page Si826x Rev. 1.3 5 Output High Current (Source)3,4 IOH Si826xAxx devices (IF =0), (tPW_IOH < 250 ns) (see Figure 3) —0.4 — A Si826xBxx devices (IF =0), (tPW_IOH < 250 ns), (VDD –VO =7.5 V) (see Figure 3) 0.5 1.8 — Output Low Current (Sink)3,4 IOL Si826xAxx devices (IF =10mA), (tPW_IOL < 250 ns) (see Figure 2) —0.6 — A Si826xBxx devices (IF =10mA), (tPW_IOL < 250 ns), (VO -GND =4.2 V) (see Figure 2) 1.2 4.0 — High-Level Output Voltage VOH Si826xAxx devices (I OUT = –100 mA) — VDD– 0.4 — V Si826xBxx devices (I OUT = –100 mA) VDD– 0.5 VDD– 0.25 — Si826xBxx devices (I OUT =0mA), (IF =0mA) —VDD — Low-Level Output Voltage VOL Si826xAxx devices (I OUT = 100 mA), (IF =10mA) — 320 — mV Si826xBxx devices (I OUT = 100 mA), (IF =10mA) — 80 200 UVLO Threshold + (Si826xxAx mode) VDDUV+ See Figure 11 on page 16. VDD rising 55.6 6.3 V UVLO Threshold – (Si826xxAx mode) VDDUV– See Figure 11 on page 16. VDD falling 4.7 5.3 6.0 V UVLO lockout hysteresis (Si826xxAx mode) VDDHYS —300 — mV Table 2. Electrical Characteristics (Continued)1 VDD =15V or 30 V, GND=0V, IF =6mA, TA = –40 to +125 °C; typical specs at 25 °C Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. See "8.Ordering Guide" on page 23 for more information. 2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF. 3. Both VO pins are required to be shorted together for 4.0 A compliance. 4. When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic inductances, which may cause over-stress conditions due to excessive ringing. 5. Guaranteed by characterization. |
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