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Q68000A8504 Datasheet(PDF) 9 Page - OSRAM GmbH |
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Q68000A8504 Datasheet(HTML) 9 Page - OSRAM GmbH |
9 / 14 page PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114 2006-01-23 9 Block Diagram Functional Description The PDSP211X block diagram is comprised of the following major blocks and registers. Display Memory consists of a 8 x 8 bit RAM block. Each of the eight 8-bit words holds the 7-bit ASCII data (bit D0-D6). The 8th bit, D7 selects 1 of the 2 pages of character ROM. D7=0 selects Page 1 of the ROM and D7=1 selects Page 2 of the ROM. A3=1. RST can be used to initialize display operation upon power up or during normal operation. When activated, RST will clear the Flash RAM and Control Word Register (00H) and reset the internal counter. All eight display memory locations will be set to 20H to show blanks in all digits. FL pin enables access to the Flash RAM. The Flash RAM will set (D0=0) or reset (D0=0) flashing of the character addressed by A0-A2. The 1 x 8 bit Control Word RAM is loaded with attribute data if A3=0. The Control Word Logic decodes attribute data for proper imple- mentation. Character ROM is designed for two pages of 128 characters each. Both pages of the ROM are Mask Programmable for custom fonts. On the standard product page one contains standard ASCII, selected European characters and some scientific symbols. Page two contains Katakana characters, more European characters, avi- onics, and other graphic symbols. The Clock Source could either be the internal oscillator (CLKSEL=1) of the device or an external clock (CLKSEL=0) could be an input from another PDSP211X display for the synchroniza- tion of blinking for multiple displays. The Display Multiplexer controls the Row Drivers so no additional logic is required for a display system. The Display has eight digits. Each digit has 35 LEDs clustered into a 5 x 7 dot matrix. Theory of Operation The PDSP211X Programmable display is designed to work with all major microprocessors. Data entry is via an eight bit parallel bus. Three bits of address route the data to the proper digit location in the RAM. Standard control signals like WR and CE allow the data to be written into the display. D0- D7 data bits are used for both ASCII and control word data input. A3 acts as the mode selector. If A3=0, D0-D7 load the RAM with control word data. If A3=1, D0-D7 will load the RAM with ASCII and page select data. In the later mode, D7=0 selects Page 1 of Character ROM and D7=1 selects Page 2 of Character ROM. For normal operation FL pin should be held high. When FL is held low, Flash RAM is accessed to set character blinking. The seven bit ASCII code is decoded by the Character ROM to generate Column data. Twenty columns worth of data is sent out each display cycle and it takes fourteen display cycles to write into eight digits. The rows are being multiplexed in two sets of seven rows each. The internal timing and control logic synchronizes the turning on of rows and presentation of column data to assure proper display operation. IDBD5068 Display Memory 8 x 8 bits D0 D4 D2 D1 D3 D6 D5 D7 Decode Logic 7-bit Code Flash RAM 8 x 1 bit Address Address Decoder A0 A1 A2 A3 WR CE FL Character Decode (4.48 kbits) ROM 1 ASCII 128 x 7 bit ASCII Character (4.48 kbits) Decode 128 x 7 bit ROM 2 Row Decoder Data Master Slave Latches Digit 0 to 8 Column Drivers 0 to 8 for Digit Column Lines Control Word ASCII OSC Counter 32 Counter 7 Counter 128 CLK I/O CLKSEL RST MUX Rate Rate Blink Row Control Logic & Row Drivers Control Timing & Logic Rows 0 Display 3 12 0 to 13 6 5 4 7 Columns 0 to 19 |
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