Multichannel, 16-Bit, 200ksps Analog-to-Digital

Converters

6

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TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Acquisition Time

External clock (Note 6)

729

ns

SCLK to DOUT Valid

100

ns

CS Fall to DOUT Enable

100

ns

CS Rise to DOUT Disable

80

ns

CS Pulse Width

100

ns

SCLK rise

CS to SCLK Setup

SCLK fall (DSP)

100

ns

SCLK rise

CS to SCLK Hold

SCLK fall (DSP)

0ns

Conversion

93

SCLK High Pulse Width

Duty cycle 45% to 55%

Data transfer

93

ns

Conversion

93

SCLK Low Pulse Width

Duty cycle 45% to 55%

Data transfer

93

ns

SCLK Period

209

ns

SCLK rise

DIN to SCLK Setup

SCLK fall (DSP)

100

ns

SCLK rise

DIN to SCLK Hold

SCLK fall (DSP)

0ns

CS Falling to DSPR Rising

100

ns

DSPR to SCLK Falling Setup

100

ns

DSPR to SCLK Falling Hold

0ns

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been

calibrated.

Note 3: Offset and reference errors nulled.

Note 4: DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels.

transfer mode.

Note 6: See Figures 10 and 17.

Note 8: Internal reference and buffer are left on between conversions.

Note 9: Defined as the change in the positive full scale caused by a ±5% variation in the nominal supply voltage.