MC145159–1

MOTOROLA

5

PIN DESCRIPTIONS

INPUT PINS

OSCin, OSCout

Oscillator Input and Oscillator Output (PDIP, SOG –

Pins 2, 3; SSOP – Pins 7, 8)

These pins form an on–chip reference oscillator when

connected to terminals of an external parallel–resonant

crystal. Frequency–setting capacitors of appropriate value

must be connected from OSCin to VSS and OSCout to

VSS. OSCin may also serve as input for an externally–gen-

erated reference signal. This signal will typically be ac

coupled to OSCin, but for larger amplitude signals (standard

CMOS logic levels), dc coupling may also be used. In the

external reference mode, no connection is required to

OSCout.

fin

Frequency Input (PDIP, SOG – Pin 10, SSOP – Pin 15)

Input to the positive edge triggered divide–by–N and di-

vide–by–A counters. fin is typically derived from a dual–

modulus prescaler and is ac coupled. This input has an

inverter biased in the linear region to allow use with ac

coupled signals as low as 500 mV peak–to–peak or direct

coupled signals swinging from VDD to VSS.

DATA

Serial Data Input (PDIP, SOG – Pin 12, SSOP – Pin 17)

Counter and control information is shifted into this input.

The last data bit entered goes into the one–bit control shift

register. A logic 1 allows the reference counter information to

be loaded into its 14–bit latch when ENB goes high. A logic 0

entered as the control bit disables the reference counter

latch. The divide–by–A/divide–by–N counter latch is loaded,

regardless of the contents of the control register, when ENB

goes high. The data entry format is shown in Figure 1.

ENB

Transparent Latch Enable (PDIP, SOG – Pin 13,

SSOP – Pin 18)

A logic high on this input allows data to be entered into the

divide–by–A/divide–by–N latch and, if the control bit is high,

into the reference counter latch. Counter programming is

unaffected when ENB is low. ENB should be kept normally

low and pulsed high to transfer data to the latches.

CLK

Shift Register Clock (PDIP, SOG – Pin 11, SSOP – Pin 16)

A low–to–high transition on this input shifts data from the

serial data input into the shift registers.

COMPONENT PINS

CR

Ramp Capacitor (PDIP, SOG – Pin 15, SSOP – Pin 20)

The capacitor connected from this pin to VSS′ is charged

linearly, at a rate determined by RR. The voltage on this

capacitor is proportional to the phase difference of the

frequencies present at the internal phase detector inputs. A

polystyrene or mylar capacitor is recommended.

RR

Ramp Current Bias Resistor (PDIP, SOG – Pin 20,

SSOP – Pin 5)

A resistor connected from this pin to VSS′ determines the

rate at which the ramp capacitor is charged, thereby affecting

the phase detector gain (see Figure 2).

CH

Hold Capacitor (PDIP, SOG – Pin 18, SSOP – Pin 3)

The charge stored on the ramp capacitor is transferred to

the capacitor connected from this pin to either VDD′ or VSS′.

The ratio of CR to CH should be large enough to have no

effect on the phase detector gain (CR > 10 CH). A low–leak-

age capacitor should be used.

RO

Output Bias Current Resistor (PDIP, SOG – Pin 1,

SSOP – Pin 6)

A resistor connected from this pin to VSS′ biases the output

N–Channel transistor, thereby setting a current sink on the

analog phase detector output. This resistor adjusts the

APDout bias current (see Figure 3).

OUTPUT PINS

APDout

Analog Phase Detector Output (PDIP, SOG – Pin 17,

SSOP – Pin 2)

This output produces a voltage that controls an external

VCO. The voltage range of this output (VDD = + 9 V) is from

below + 0.5 V to + 8 V or more. The source impedance of this

output is the equivalent of a source follower with an exter-

nally variable source resistor. The source resistor depends

upon the output bias current controlled by the output bias

current resistor, RO. The bias current is adjustable from

0.01 mA to 0.5 mA. The output voltage is not more than

1.05 V below the sampled point on the ramp. With a constant

sample of the ramp voltage at 9 V and the hold capacitor of

50 pF, the instantaneous output ripple is about 5 mV peak–

to–peak.

Figure 1. Data Entry Format

LATCHED WHEN

CONTROL BIT = 1

LATCHED WHEN

CONTROL BIT = 0

LAST

BIT

A0

LSB

A6

MSB

N0

LSB

N9

MSB

R0

LSB

R13

MSB

SHIFT

REGISTER

OUT

DATA IN

CONTROL BIT