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71V416S15YG Datasheet(PDF) 5 Page - Integrated Device Technology

Part # 71V416S15YG
Description  3.3V CMOS Static RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

71V416S15YG Datasheet(HTML) 5 Page - Integrated Device Technology

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6.42
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
5
71V416S/L10
71V416S/L12
71V416S/L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
10
____
12
____
15
____
ns
tAA
Address Access Time
____
10
____
12
____
15
ns
tACS
Chip Select Access Time
____
10
____
12
____
15
ns
tCLZ(1)
Chip Select Low to Output in Low-Z
4
____
4
____
4
____
ns
tCHZ(1)
Chip Select High to Output in High-Z
____
5
____
6
____
7ns
tOE
Output Enable Low to Output Valid
____
5
____
6
____
7ns
tOLZ(1)
Output Enable Low to Output in Low-Z
0
____
0
____
0
____
ns
tOHZ(1)
Output Enable High to Output in High-Z
____
5
____
6
____
7ns
tOH
Output Hold from Address Change
4
____
4
____
4
____
ns
tBE
Byte Enable Low to Output Valid
____
5
____
6
____
7ns
tBLZ(1)
Byte Enable Low to Output in Low-Z
0
____
0
____
0
____
ns
tBHZ(1)
Byte Enable High to Output in High-Z
____
5
____
6
____
7ns
WRITE CYCLE
tWC
Write Cycle Time
10
____
12
____
15
____
ns
tAW
Address Valid to End of Write
8
____
8
____
10
____
ns
tCW
Chip Select Low to End of Write
8
____
8
____
10
____
ns
tBW
Byte Enable Low to End of Write
8
____
8
____
10
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Address Hold from End of Write
0
____
0
____
0
____
ns
tWP
Write Pulse Width
8
____
8
____
10
____
ns
tDW
Data Valid to End of Write
5
____
6
____
7
____
ns
tDH
Data Hold Time
0
____
0
____
0
____
ns
tOW(1)
Write Enable High to Output in Low-Z
3
____
3
____
3
____
ns
tWHZ(1)
Write Enable Low to Output in High-Z
____
6
____
7
____
7ns
3624 tbl 10
Timing Waveform of Read Cycle No. 1(1,2,3)
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
DATAOUT
ADDRESS
3624 drw 06
tRC
tAA
tOH
DATAOUT VALID
PREVIOUS DATAOUT VALID
tOH
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.


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