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71V65803Z100BGGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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71V65803Z100BGGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 26 page  OCTOBER 2008 DSC-5304/08 1 ©2008 Integrated Device Technology, Inc. Pin Description Summary Description The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit (9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus cycleswhenturningthebusaroundbetweenreadsandwrites,orwritesand reads. Thus, they have been given the name ZBTTM, or Zero Bus Turn- around. Features ◆ ◆ ◆ ◆ ◆ 256K x 36, 512K x 18 memory configurations ◆ ◆ ◆ ◆ ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ◆ ◆ ◆ ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ ◆ ◆ ◆ ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ ◆ ◆ ◆ ◆ Single R/W (READ/WRITE) control pin ◆ ◆ ◆ ◆ ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ ◆ ◆ ◆ ◆ 4-word burst capability (interleaved or linear) ◆ ◆ ◆ ◆ ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ ◆ ◆ ◆ ◆ Three chip enables for simple depth expansion ◆ ◆ ◆ ◆ ◆ 3.3V power supply (±5%) ◆ ◆ ◆ ◆ ◆ 3.3V I/O Supply (VDDQ) ◆ ◆ ◆ ◆ ◆ Power down controlled by ZZ input ◆ ◆ ◆ ◆ ◆ Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array(fBGA). A0-A18 Address Inputs Input Synchronous CE1 , CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1 , BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5304 tbl 01 256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs IDT71V65603/Z IDT71V65803/Z AddressandcontrolsignalsareappliedtotheSRAMduringoneclock cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite. TheIDT71V65603/5803containdataI/O,addressandcontrolsignal registers.Outputenableistheonlyasynchronoussignalandcanbeused to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803 tobesuspendedaslongasnecessary.Allsynchronousinputsareignored when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT71V65603/5803 have an on-chip burst counter. In the burst mode, the IDT71V65603/5803 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V65603/5803 SRAM utilize IDT's latest high-performance CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) . ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc. |
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