71V424S15YG datasheet(6/9 Pages) IDT

Part #	71V424S15YG

Description	3.3V CMOS Static RAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM

4 Meg (512K x 8-bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle No. 2(1, 2, 4)

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

Timing Waveform of Read Cycle No. 1(1)

ADDRESS

3622 drw 06

OE

CS

DATAOUT

(5)

DATAOUT VALID

HIGH IMPEDANCE

tAA

tRC

tOE

tACS

tOLZ

tCHZ

tCLZ

(3)

tOHZ

VCC SUPPLY

CURRENT

tPU

tPD

ICC

ISB

DATAOUT

ADDRESS

3622 drw 07

tRC

tAA

tOH

DATAOUT VALID

PREVIOUS DATAOUT VALID

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