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709379L12PFGI Datasheet(PDF) 7 Page - Integrated Device Technology |
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709379L12PFGI Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 16 page  6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 7 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza- tion, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL. AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VCC = 5V ± 10%) 709379/69L7 Com'l Only 709379/69L9 Com'l & Ind 709379/69L12 Com'l Only Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tCYC1 Clock Cycle Time (Flow-Through)(2) 22 ____ 25 ____ 30 ____ ns tCYC2 Clock Cycle Time (Pipelined)(2) 12 ____ 15 ____ 20 ____ ns tCH1 Clock High Time (Flow-Through)(2) 7.5 ____ 12 ____ 12 ____ ns tCL1 Clock Low Time (Flow-Through)(2) 7.5 ____ 12 ____ 12 ____ ns tCH2 Clock High Time (Pipelined)(2) 5 ____ 6 ____ 8 ____ ns tCL2 Clock Low Time (Pipelined)(2) 5 ____ 6 ____ 8 ____ ns tR Clock Rise Time ____ 3 ____ 3 ____ 3ns tF Clock Fall Time ____ 3 ____ 3 ____ 3ns tSA Address Setup Time 4 ____ 4 ____ 4 ____ ns tHA Address Hold Time 0 ____ 1 ____ 1 ____ ns tSC Chip Enable Setup Time 4 ____ 4 ____ 4 ____ ns tHC Chip Enable Hold Time 0 ____ 1 ____ 1 ____ ns tSB Byte Enable Setup Time 4 ____ 4 ____ 4 ____ ns tHB Byte Enable Hold Time 0 ____ 1 ____ 1 ____ ns tSW R/W Setup Time 4 ____ 4 ____ 4 ____ ns tHW R/W Hold Time 0 ____ 1 ____ 1 ____ ns tSD Input Data Setup Time 4 ____ 4 ____ 4 ____ ns tHD Input Data Hold Time 0 ____ 1 ____ 1 ____ ns tSAD ADS Setup Time 4 ____ 4 ____ 4 ____ ns tHAD ADS Hold Time 0 ____ 1 ____ 1 ____ ns tSCN CNTEN Setup Time 4 ____ 4 ____ 4 ____ ns tHCN CNTEN Hold Time 0 ____ 1 ____ 1 ____ ns tSRST CNTRST Setup Time 4 ____ 4 ____ 4 ____ ns tHRST CNTRST Hold Time 0 ____ 1 ____ 1 ____ ns tOE Output Enable to Data Valid ____ 7.5 ____ 9 ____ 12 ns tOLZ Output Enable to Output Low-Z(1) 2 ____ 2 ____ 2 ____ ns tOHZ Output Enable to Output High-Z(1) 17 17 17 ns tCD1 Clock to Data Valid (Flow-Through)(2) ____ 18 ____ 20 ____ 25 ns tCD2 Clock to Data Valid (Pipelined)(2) ____ 7.5 ____ 9 ____ 12 ns tDC Data Output Hold After Clock High 2 ____ 2 ____ 2 ____ ns tCKHZ Clock High to Output High-Z(1) 292929 ns tCKLZ Clock High to Output Low-Z(1) 2 ____ 2 ____ 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 28 ____ 35 ____ 40 ns tCCS Clock-to-Clock Setup Time ____ 10 ____ 15 ____ 15 ns 4845 tbl 11 |
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