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709289L7PFG8 Datasheet(PDF) 3 Page - Integrated Device Technology

Part # 709289L7PFG8
Description  HIGH-SPEED 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

709289L7PFG8 Datasheet(HTML) 3 Page - Integrated Device Technology

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6.42
IDT709289L
High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table I—Read/Write and Enable Control(1,2,3)
OE
CLK
CE0
CE1
UB
LB
R/W
Upper Byte
I/O8-15
Lower Byte
I/O0-7
Mode
X
↑
H
X
X
X
X
High-Z
High-Z
Deselected—Power Down
X
↑
X
L
X
X
X
High-Z
High-Z
Deselected—Power Down
X
↑
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
X
↑
LH
LH
L
DATAIN
High-Z
Write to Upper Byte Only
X
↑
LH
H
L
L
High-Z
DATAIN
Write to Lower Byte Only
X
↑
LH
L
L
L
DATAIN
DATAIN
Write to Both Bytes
L
↑
LH
LH
H
DATAOUT
High-Z
Read Upper Byte Only
L
↑
LH
H
L
H
High-Z
DATAOUT
Read Lower Byte Only
L
↑
LH
L
L
H
DATAOUT
DATAOUT
Read Both Bytes
H
X
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
4842 tbl 02
Pin Names
Left Port
Right Port
Names
CE0L
, CE1L
CE0R
, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A15L
A0R - A15R
Address
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
CLKL
CLKR
Clock
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
ADSL
ADSR
Address Strobe
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
FT
/PIPEL
FT
/PIPER
Flow-Through/Pipeline
VCC
Power
GND
Ground
4842 tbl 01


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