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71V547S90PFG Datasheet(PDF) 10 Page - Integrated Device Technology |
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71V547S90PFG Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 20 page  10 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges NOTE: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Read Operation With Clock Enable Used(1) NOTE: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Write Operation With Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BW x OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 H L L L X L Q0 Address A0 Read out, Load A1 n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus n+5 A2 H L L L X L Q1 Address A1 Read out, Load A2 n+6 A3 H L L L X L Q2 Address A2 Read out, Load A3 n+7 A4 H L L L X L Q3 Address A3 Read out, Load A4 3822 tbl 16 Cycle Address R/W ADV/LD CE(2) CEN BW x OE I/O Comments n A0 L L L L L X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 L L L L L X D0 Write data D0, Load A1 n+3 X X X X H XXX Clock Ignored n+4 X X X X H XXX Clock Ignored n+5 A2 L L L L L X D1 Write data D1, Load A2 n+6 A3 L L L L L X D2 Write data D2, Load A3 n+7 A4 L L L L L X D3 Write data D3, Load A4 3822 tbl 17 |
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