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UPSD3213AV-40U6T Datasheet(PDF) 7 Page - STMicroelectronics

Part # UPSD3213AV-40U6T
Description  Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3213AV-40U6T Datasheet(HTML) 7 Page - STMicroelectronics

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µPSD323X
PSD MODULE . . . . . . .... . . . .... .... .. . .... .. . .... . ... .. .. .. .... . . . ... . . . . . . . . . . . . 102
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . .. . . . . . . . . . . . . . ... .. . .... . . 102
PSD MODULE Block Diagram (Figure 50.). . . . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... . . 103
In-System Programming (ISP). . . .... . ... .. . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... . . 104
Methods of Programming Different Functional Blocks of the PSD MODULE (Table 83.) . . . . . . . 104
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .... ... . ... .. . . ... .. . .... 105
PSDsoft Express Development Tool (Figure 51.) . . . . ... . . . . . . . . . . . . . ... . ... . . .. .. .. .. 105
PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . .... . . . . .. . . . . . . . . .... 106
Register Address Offset (Table 84.) . . . . . . . . . . . . .... .... .. . .... .. . . . . . . ... .. . .... . . 106
PSD MODULE DETAILED OPERATION . .... . . ... .. ... .. .. . . . . . . . . . . . . . . .... . . ... .. ..107
MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...107
Primary Flash Memory and Secondary Flash memory Description. . . . . . . . . . . . . . . . . . . . . ...107
Memory Block Select Signals . . . .... . ... .. . . ... ... . ... .. . . ... .. . . ... . ... .. .. ... ..107
Instructions . . . . . . . . . . . . . . . . . . . . . .... . . ... .. .... ... . . . . . . . . . . . . . . . . . .. . ... .. ..108
Instructions (Table 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . ... . ... .. . . ... .. . .... 109
Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. 110
READ. . . . . . . . . . . . . . . . . . . . . . . . . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. .. 110
Status Bit (Table 86.). . . . . .... . . . . .. . . . . . . . . . . . . . ... ... . . . . . . . . . . ... .. .. . . . . . . . . 111
Programming Flash Memory . . . . . . . . . . . . . . . . . .... . ... .. . . . . .... . . . . .. . . . . . . . . .... 112
Data Polling Flowchart (Figure 52.) . . . . . .... .. . .... . ... .. .. .. .... . . . ... . . . . . . . . . . . . 112
Data Toggle Flowchart (Figure 53.). . . . . . . . . . . . . . . . . . . .... . . . .... .... .. . .... .. . .... 113
Erasing Flash Memory. . . . . . . . . . . . . .... . . ... .. ... .. .. . . . . . . . . . . . . . . .... . . ... .. ..114
Specific Features. . . . . . . . . . . . . . . . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. ..115
Sector Protection/Security Bit Definition – Flash Protection Register (Table 87.) . . . .... . ... ..115
Sector Protection/Security Bit Definition – Secondary Flash Protection Register (Table 88.) . . . . 115
SRAM . . . . . . . . . .... . ... ... . . . . . . . . ... .. .. ... . . . .... . . . .... .... .. . .... . . . . ...116
Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . .... . . . .... . ... .. . . ... .. . .... 116
Priority Level of Memory and I/O Components in the PSD MODULE (Figure 54.) . . . . . . . . .... 117
VM Register (Table 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Separate Space Mode (Figure 55.) . . . . . . . . . . . . . . . . . . . .... .... ... . . . . . . . . ... .. . . ... 118
Combined Space Mode (Figure 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... ..119
Page Register (Figure 57.) . . . . . .... . ... .. . . ... ... . ... .. . . ... .. . . ... . ... .. .. ... ..119
PLDs .... . ... ... . . . . . . . . . . . . . . . ... . . . .... . ... .. .. .. . . . . . . . . . . . . ... . . . . . . .. . .... 120
DPLD and CPLD Inputs (Table 90.) . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. .. 120
The Turbo Bit in PSD MODULE . . . . . . . . . . . . . . . . . ... . . . . . . . . . .... ... . . . . . . . . . . . . . . 120
PLD Diagram (Figure 58.) . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...121
Decode PLD (DPLD) . . . . . . .... . . .. .. ... .. .. .. .. . . . . . . ... . . . . . . . . . ... .. .. ... .. .. 122
DPLD Logic Array (Figure 59.) . . .... . ... .. . . . . .... . ... .. . . ... .. . . . . . . ... .. . . ... ..122
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...123
Macrocell and I/O Port (Figure 60.) . . . . . . . . . . . . . . . ... . . . . . . . . . .... ... . ... . . .. .. .. .. 123
Output Macrocell Port and Data Bit Assignments (Table 91.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124


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