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IDT71T7570285PFI Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71T7570285PFI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 26 page  APRIL 2004 DSC-5319/08 1 ©2004 Integrated Device Technology, Inc. A0-A19 Add ress Inputs Input Synchronous CE1, CE2, CE2 Chip Enable s Input Synchronous OE Output Enable Input Asynchronous R/ W Re ad/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Sele cts Input Synchronous CLK Clock Input N/A ADV/ LD Ad vance Burst Address/Load New Ad dress Input Synchronous LBO Linear/Interleaved Burst Orde r Input Static TMS Test Mode Select Input N/A TDI Test Data Input Input N/A TCK Test Clock Input N/A TDO Test Data Output Output N/A TRST JTAG Reset (Optional) Input Asynchronous ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP4 Data Input/Output I/O Synchronous VDD, VDDQ Co re Po wer, I/O Power Sup ply Static VSS Ground Sup ply Static 5319 tbl 01 Pin Description Summary The IDT71T75702/902 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable ( CEN)pinallowsoperationoftheIDT71T75702/902 to be suspended as long as necessary. All synchronous inputs are ignored when CENishighandtheinternaldeviceregisterswillholdtheir previous values. There are three chip enable pins ( CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not assertedwhenADV/ LDislow,nonewmemoryoperationcanbeinitiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after the chip is deselected or a write isinitiated. The IDT71T75702/902 have an on-chip burst counter. In the burst mode, the IDT71T75702/902 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/ LD signal is used to load a new externaladdress(ADV/ LD=LOW)orincrementtheinternalburstcounter (ADV/ LD = HIGH). The IDT71T75702/902 SRAMs utilize IDT’s high-performance CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array (BGA). Features x x x x x 512K x 36, 1M x 18 memory configurations x x x x x Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) x x x x x ZBTTM Feature - No dead cycles between write and read cycles x x x x x Internally synchronized output buffer enable eliminates the need to control OE OE OE OE OE x x x x x Single R/ W W W W W (READ/WRITE) control pin x x x x x 4-word burst capability (Interleaved or linear) x x x x x Individual byte write ( BW BW BW BW BW1 - BW BW BW BW BW4) control (May tie active) x x x x x Three chip enables for simple depth expansion x x x x x 2.5V power supply (±5%) x x x x x 2.5V (±5%) I/O Supply (VDDQ) x x x x x Power down controlled by ZZ input x x x x x Boundary Scan JTAG Interface (IEEE 1149.1 Compliant) x x x x x Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) Description The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit (18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround. AddressandcontrolsignalsareappliedtotheSRAMduringoneclock cycle, and on the next clock cycle the associated data cycle occurs, be it read or write. IDT71T75702 IDT71T75902 512K x 36, 1M x 18 2.5V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs FEBRUARY 2009 |
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