MC44460

11

MOTOROLA ANALOG IC DEVICE DATA

to prevent the PIP from interfering with the main picture

sync pulses.

PIP Y Position Register

Sub–address = 07h

Y Position Bits (YPS0–5) – D0–D5

Moves the PIP start position from the top to the bottom

edge of the display in 64 steps. There is protection circuitry to

prevent the PIP from interfering with the main picture sync

pulses.

PIP Chroma Level Register

Sub–address = 08h

Chroma (C0–5) – D0–D5

The color of the PIP can be adjusted to suit viewer

preference by setting the value stored in these bits. A total of

64 steps varies the color from no color to maximum. This

control acts in conjunction with the auto phase control.

PIP Tint Level Register

Sub–address = 09h

Tint (T0–5) – D0–D5

An auto phase control compares the main color burst to

the internally generated pseudo color burst so that the tints

are matched. In addition to this, the tint of the PIP can be

varied

±10° in a total of 64 steps by changing the value of

these bits to suit viewer preference.

PIP Luma Delay Register

Sub–address = 0Ah

Y Delay (YDL0–2) – D0–D2

Since the Chroma passes through a bandpass filter and

the color decoder, it is delayed with respect to the Luma

signal. Therefore, to time match the Luma and Chroma these

bits are set to a single value determined to be correct in the

application.

Pip Fill/Test Register

Sub–address = 0Ch

PIP Fill Bits (PIPFILL0–1) – D0–D1

May be used to fill the PIP with one of three selectable

solid colors

Test Register Bits (INTC0 and MACR0) – D6–D7

Used for production test only.

I2C REGISTER TABLE

Sub–

address

Data Bit

Sub–

address

D7

D6

D5

D4

D3

D2

D1

D0

00

RPS3

RPS2

RPS1

RPS0

–

WPS2

WPS1

WPS0

01

–

–

–

VFON

PSD3

PSD2

PSD1

PSD0

02

–

–

–

–

–

BC2

BC1

BC0

03

MHP0

MVP0

–

–

–

ITM2

ITM1

ITM0

04

PSEL0

MSEL0

PSI90

STIL0

–

–

–

–

05

–

–

–

PBL0

–

–

–

PON0

06

–

–

XPS5

XPS4

XPS3

XPS2

XPS1

XPS0

07

–

–

YPS5

YPS4

YPS3

YPS2

YPS1

YPS0

08

–

–

C5

C4

C3

C2

C1

C0

09

–

–

T5

T4

T3

T2

T1

T0

0A

–

–

–

–

–

YDL2

YDL1

YDL0

0B

–

–

–

–

–

–

–

–

0C

–

–

–

–

–

–

–

–