MOTOROLA CMOS LOGIC DATA

1

MC14583B

Dual Schmitt Trigger

The MC14583B is a dual Schmitt trigger constructed with complementary

P–channel and N–channel MOS devices on a monolithic silicon substrate.

Each Schmitt trigger is functionally independent except for a common

3–state input and an internally–connected Exclusive OR output for use in

line receiver applications. Trigger levels are adjustable through the positive,

negative, and common terminals with the use of external resistors.

Applications include the speed–up of a slow waveform edge in interface

receivers, level detectors, etc.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Single Supply Operation

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Resistor Adjustable Trigger Levels

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, Vout Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

Iin, Iout

Input or Output Current (DC or Transient),

per Pin

± 10

mA

PD

Power Dissipation, per Package†

500

mW

Tstg

Storage Temperature

– 65 to + 150

_C

TL

Lead Temperature (8–Second Soldering)

260

_C

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/

_C From 100_C To 125_C

LOGIC DIAGRAM

POSITIVE A

6 5

NEGATIVE A

7 COMMON A

Bout

9

Ain

12

Bout

10

EXCLUSIVE OR

14

Aout

11

Aout

4

13

15

Bin

POSITIVE B2

2 3

NEGATIVE B

1 COMMON B

3–STATE

OUTPUT DISABLE

VDD = PIN 16

VSS = PIN 8

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 3

1/94

MC14583B

L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP

Plastic

MC14XXXBCL

Ceramic

MC14XXXBD

SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

BLOCK DIAGRAM

TRUTH TABLE

Inputs

Outputs

A

B

Dis Aout Aout Bout Bout

0

0

0

0

Z

0

Z

0

0

0

1

0

1

0

1

0

0

1

0

0

Z

1

Z

1

0

1

1

0

1

1

0

1

1

0

0

1

Z

0

Z

1

1

0

1

1

0

0

1

1

1

1

0

1

Z

1

Z

0

1

1

1

1

0

1

0

0

Z = High impedance at output

VDD = PIN 16

VSS = PIN 8

9

13

15

12

10

14

11

4

APos ANeg ACom

BPos BNeg BCom

Ain

Bin

Dis

Bout

Bout

Aout

Aout

6

5

7

2

3

1