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AD9694BCPZ-500 Datasheet(PDF) 2 Page - Analog Devices |
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AD9694BCPZ-500 Datasheet(HTML) 2 Page - Analog Devices |
2 / 101 page AD9694 Data Sheet Rev. 0 | Page 2 of 101 TABLE OF CONTENTS \Features.......................................................................................................1 Applications ................................................................................................1 Functional Block Diagram.......................................................................1 Revision History.........................................................................................2 General Description..................................................................................3 Product Highlights ....................................................................................3 Specifications ..............................................................................................4 DC Specifications..................................................................................4 AC Specifications...................................................................................5 Digital Specifications ............................................................................7 Switching Specifications.......................................................................8 Timing Specifications...........................................................................9 Absolute Maximum Ratings..................................................................11 Thermal Resistance.............................................................................11 ESD Caution.........................................................................................11 Pin Configuration and Function Descriptions ..................................12 Typical Performance Characteristics....................................................14 Equivalent Circuits ..................................................................................21 Theory of Operation ...............................................................................23 ADC Architecture...............................................................................23 Analog Input Considerations............................................................23 Voltage Reference ................................................................................24 DC Offset Calibration ........................................................................25 Clock Input Considerations ..............................................................25 ADC Overrange and Fast Detect..........................................................28 ADC Overrange...................................................................................28 Fast Threshold Detection (FD_A, FD_B, FD_C, and FD_D)....28 Signal Monitor ................................................................................ 29 SPORT Over JESD204B............................................................. 29 Digital Downconverter (DDC)..................................................... 32 DDC I/Q Input Selection .......................................................... 32 DDC I/Q Output Selection ....................................................... 32 DDC General Description ........................................................ 32 Frequency Translation ................................................................... 38 General Description................................................................... 38 DDC NCO and Mixer Loss and SFDR.................................... 39 Numerically Controlled Oscillator........................................... 39 FIR Filters ........................................................................................ 41 Overview ..................................................................................... 41 Half-Band Filters ........................................................................ 42 DDC Gain Stage ......................................................................... 43 DDC Complex to Real Conversion ......................................... 43 DDC Example Configurations ................................................. 44 Digital Outputs ............................................................................... 49 Introduction to the JESD204B Interface ................................. 49 Setting Up the AD9694 Digital Interface................................ 49 Functional Overview ................................................................. 51 JESD204B Link Establishment ................................................. 51 Physical Layer (Driver) Outputs .............................................. 52 JESD204B Tx Converter Mapping........................................... 53 Configuring the JESD204B Link.............................................. 55 Latency............................................................................................. 59 End-to-End Total Latency......................................................... 59 Multichip Synchronization............................................................ 60 SYSREF± Set up and Hold Window Monitor ........................ 62 Test Modes....................................................................................... 64 ADC Test Modes ........................................................................ 64 JESD204B Block Test Modes .................................................... 65 Serial Port Interface........................................................................ 67 Configuration Using the SPI..................................................... 67 Hardware Interface..................................................................... 67 SPI Accessible Features.............................................................. 67 Memory Map .................................................................................. 68 Reading the Memory Map Register Table............................... 68 Memory Map .................................................................................. 69 Register Table Summary............................................................ 69 Memory Map Register Table—Details .................................... 75 Applications Information ............................................................ 100 Power Supply Recommendations........................................... 100 Exposed Pad Thermal Heat Slug Recommendations.......... 100 AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) ..... 100 Outline Dimensions..................................................................... 101 Ordering Guide ........................................................................ 101 REVISION HISTORY 10/2016—Revision 0: Initial Version |
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