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S-8239AAC-M6T1U Datasheet(PDF) 8 Page - Seiko Instruments Inc |
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S-8239AAC-M6T1U Datasheet(HTML) 8 Page - Seiko Instruments Inc |
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8 / 30 page  OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK S-8239A Series Rev.1.4_03 8 Test Circuits Caution Unless otherwise specified, the output voltage levels "H" and "L" at the DO pin (VDO) are judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the DO pin level with respect to VSS. 1. Overcurrent 1 detection voltage, overcurrent 2 detection voltage, overcurrent release voltage, UVLO detection voltage (Test condition 1, test circuit 1) 1. 1 Active "L" The overcurrent 1 detection voltage (VDIOV1) is defined as the voltage V2 whose delay time for changing VDO from "H" to "L" lies between the minimum and the maximum value of the overcurrent 1 detection delay time after the voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V. The overcurrent 2 detection voltage (VDIOV2) is defined as the voltage V2 whose delay time for changing VDO from "H" to "L" lies between the minimum and the maximum value of the overcurrent 2 detection delay time after the voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V. The overcurrent release voltage (VRIOV) is defined as the voltage V3 at which VDO goes from "L" to "H" after decreasing V2 to 0 V and the voltage V3 is increased gradually from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V. The UVLO detection voltage (VUVLO) is defined as the voltage V1 at which VDO goes from "H" to "L" after the voltages V1 and V3 are decreased gradually from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V. 1. 2 Active "H" The overcurrent 1 detection voltage (VDIOV1) is defined as the voltage V2 whose delay time for changing VDO from "L" to "H" lies between the minimum and the maximum value of the overcurrent 1 detection delay time after the voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V. The overcurrent 2 detection voltage (VDIOV2) is defined as the voltage V2 whose delay time for changing VDO from "L" to "H" lies between the minimum and the maximum value of the overcurrent 2 detection delay time after the voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V. The overcurrent release voltage (VRIOV) is defined as the voltage V3 at which VDO goes from "H" to "L" after decreasing V2 to 0 V and the voltage V3 is increased gradually from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V. The UVLO detection voltage (VUVLO) is defined as the voltage V1 at which VDO goes from "L" to "H" after the voltages V1 and V3 are decreased gradually from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V. 2. Overcurrent 3 detection voltage (Overcurrent 3 detection function "available") (Test condition 1, test circuit 1) 2. 1 Active "L" The overcurrent 3 detection voltage (VDIOV3) is defined as the voltage V2 whose delay time for changing VDO from "H" to "L" lies between the minimum and the maximum value of the overcurrent 3 detection delay time after the voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V. 2. 2 Active "H" The overcurrent 3 detection voltage (VDIOV3) is defined as the voltage V2 whose delay time for changing VDO from "L" to "H" lies between the minimum and the maximum value of the overcurrent 3 detection delay time after the voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V. 3. Current consumption during normal operation, current consumption during UVLO operation (Test condition 2, test circuit 2) The current consumption during normal operation (IOPE) is the current that flows through the VDD pin (IDD) under the set conditions of V1 = 3.5 V, V2 = 0 V. The current consumption during UVLO operation (IUVLO) is IDD under the set conditions of V1 = V2 = 1.5 V. 4. Internal resistance between VM pin and VSS pin (Test condition 3, test circuit 3) The internal resistance between the VM pin and the VSS pin (RVMS) is the resistance between the VM pin and the VSS pin under the set condition of V1 = V2 = V3 = 3.5 V. |
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