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S-8239AAA-M6T1U Datasheet(PDF) 7 Page - Seiko Instruments Inc |
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S-8239AAA-M6T1U Datasheet(HTML) 7 Page - Seiko Instruments Inc |
7 / 30 page OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK Rev.1.4_03 S-8239A Series 7 2. Ta = −40°C to +85°C *1 Table 6 (Ta = −40°C to +85°C *1 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Condition Test Circuit Detection Voltage Overcurrent 1 detection voltage VDIOV1 − VDIOV1 − 0.021 VDIOV1 VDIOV1 + 0.021 V 1 1 Overcurrent 2 detection voltage *2 VDIOV2 − VDIOV2 − 0.130 VDIOV2 VDIOV2 + 0.130 V 1 1 Overcurrent 3 detection voltage VDIOV3 Overcurrent 3 detection function "available" 0.70 1.20 1.70 V 1 1 UVLO detection voltage VUVLO − 1.85 2.00 2.15 V 1 1 Release Voltage Overcurrent release voltage VRIOV VDD criteria, VDD = 3.5 V 0.5 1.2 1.7 V 1 1 Input Voltage, Operation Voltage Operation voltage between VDD pin and VSS pin VDSOP Output logic is determined *3 1.5 − 8 V − − Current Consumption Current consumption during normal operation IOPE VDD = 3.5 V, VVM = 0 V 0.7 3.5 8.0 μA 2 2 Current consumption during UVLO operation IUVLO VDD = VVM = 1.5 V 0.5 3.0 7.0 μA 2 2 Internal Resistance Internal resistance between VM pin and VSS pin RVMS VDD = VVM = 3.5 V 150 300 450 k Ω 3 3 Output Resistance (Active "L") DO pin resistance "L" RDOL VDD = VVINI = 3.5 V, VDO = 0.5 V 1.2 5 15 k Ω 4 4 Output Resistance (Active "H") DO pin resistance "L" RDOL VDD = 3.5 V, VVINI = 0 V VDO = 0.5 V 1.2 5 15 k Ω 4 4 Delay Time Overcurrent 1 detection delay time tDlOV1 − tDIOV1 × 0.2 tDIOV1 tDIOV1 × 1.8 ms 5 5 Overcurrent 2 detection delay time tDlOV2 − tDIOV2 × 0.2 tDIOV2 tDIOV2 × 1.8 ms 5 5 Overcurrent 3 detection delay time tDlOV3 Overcurrent 3 detection function "available" 56 280 504 μs 5 5 UVLO detection delay time tUVLO − 0.98 4.90 8.82 s 5 5 *1. Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design, not tested in production. *2. Even if overcurrent 1 detection voltage and overcurrent 2 detection voltage are in the same range, VDIOV1 is lower than VDIOV2. *3. It indicates that DO pin output logic is determined. |
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