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TPS26601RHFR Datasheet(PDF) 8 Page - Texas Instruments |
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TPS26601RHFR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 49 page  8 TPS2660 SLVSDG2A – JULY 2016 – REVISED AUGUST 2016 www.ti.com Product Folder Links: TPS2660 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.6 Timing Requirements –40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted)) MIN NOM MAX UNIT IN and UVLO INPUT UVLO_tON(dly) UVLO turnon delay UVLO ↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dvdt) = open 250 µs UVLO ↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF] 250 + 14.5 × C(dvdt) µs UVLO_toff(dly) UVLO turnoff delay UVLO ↓ (100 mV below V(UVLOF)) to FLT↓ 10 µs SHUTDOWN CONTROL INPUT (SHDN) tSD(dly) SHUTDOWN exit delay SHDN ↑ to V(OUT) = 100 mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF] 250 + 14.5 × C(dvdt) µs SHDN ↑ to V(OUT) = 100 mV, C(dvdt) = open 250 µs SHUTDOWN entry delay SHDN ↓ (below V(SHUTF)) to FLT↓ 10 µs OVER VOLTAGE PROTECTION INPUT (OVP) tOVP(dly) OVP exit delay OVP ↓ (20 mV below V(OVPF)) to V(OUT) = 100 mV, TPS26600 & TPS26601 only 200 µs OVP disable delay OVP ↑ (20 mV above V(OVPR)) to FLT↓, TPS26600 and TPS26601 only 6 µs CURRENT LIMIT tFASTTRIP(dly) Fast-trip comparator delay I(OUT) > I(FASTRIP) 250 ns REVERSE PROTECTION COMPARATOR tREV(dly) Reverse protection comparator delay (V(IN) – V(OUT))↓ (100 mV overdrive below V(REVTH)) to internal FET turn OFF 1.5 µs (V(IN) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT ↓ 45 tFWD(dly) (V(IN) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT ↑ 70 THERMAL SHUTDOWN tretry Retry delay in TSD 512 ms OUTPUT RAMP CONTROL (dVdT) tdVdT Output ramp time SHDN ↑ to V(OUT) = 23.9 V, with C(dVdT) = 47 nF 10 ms SHDN ↑ to V(OUT) = 23.9 V, with C(dVdT) = open 1.6 FAULT FLAG (FLT) tCB(dly) FLT assertion delay in circuit breaker mode MODE = OPEN, delay from I(OUT) > I(OL) to FLT↓ 4 ms tCBretry(dly) Retry delay in circuit breaker mode MODE = OPEN 540 ms tPGOODF PGOOD delay (de- glitch) time Falling edge 875 µs tPGOODR Rising edge, C(dVdT) = open 1400 Rising egde, C(dVdT) ≥ 10 nF, [C(dvdt) in nF] 875 + 20 × C(dVdT) |
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