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TAS5110 Datasheet(PDF) 9 Page - Texas Instruments |
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TAS5110 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 20 page TAS5110 SLES028A – MAY 2002 – REVISED SEPTEMBER 2002 9 www.ti.com device operation power sequences system power-up/power-down sequencing The recommended power-up/power-down sequence is shown in Figure 3. For proper operation the RESET signal should be kept low when both DVDD and output power (PVDDA1, PVDDA2, PVDDB1, and PVDDB2) are being applied. The RESET signal should remain low for at least 1 ms after output power is applied. > 1 ms DVDD† PWDN PVDDA2 PVDDB2 RESET > 1 ms > 100 µs > 100 µs PVDDA1 PVDDB1 † For most applications, it is recommended that the PWDN pin be connected directly to the DVDD pin. Figure 3. Power-Up/Power-Down Sequence RESET function The device is put into a reset condition when the (active low) RESET signal is asserted. While in the reset state, the input H-bridge control signals consisting of PWM_AP, PWM_AM, PWM_BP, and PWM_BM are ignored, and the H-bridge MOSFETs are placed in a state where OUTPUTA and OUTPUTB are both low. Asserting the RESET signal low also causes the short circuit protection latch to be reset. The RESET signal is normally connected to the VALID signal from the TAS50xx. reinitialization sequence Proper initial conditions for this device include asserting the RESET signal until the reset operation has completed (1 ms). Additionally, when using this device with the TAS50xx controller, this function can be accomplished by asserting the reset pin on the TAS50xx during the reset sequence (see Figure 3). audio application considerations optimal power transfer for H-bridge The TAS5110 is a power H-bridge that is designed to deliver a maximum of 50 W RMS into a 6- Ω load. In order to achieve 50 W into 6 Ω, the system designer must provide an adequate thermal design. See the Thermal Methodology for the 32-Pin DAD Package 50 W, 6- Ω Test and the Thermal Methodology for the 32-Pin DAP Package 50 W, 6- Ω sections for a discussion of possible thermal solutions. Careful attention must be given to the value of the high-voltage power supply level for a given load resistance. See recommended operating conditions. See the Maximum Available Power at Common Load Impedances for Both DAP and DAD Packages section. |
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