MC54/74HC245A

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

tPLH,

tPHL

Maximum Propagation Delay, A to B, B to A

(Figures 1 and 3)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Direction or Output Enable to A or B

(Figures 2 and 4)

2.0

4.5

6.0

110

22

19

140

28

24

165

33

28

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to A or B

(Figures 2 and 4)

2.0

4.5

6.0

110

22

19

140

28

24

165

33

28

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

Cin

Maximum Input Capacitance (Pin 1 or Pin 19)

—

10

10

10

pF

Cout

Maximum Three–State I/O Capacitance

(I/O in High–Impedance State)

—

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Transceiver Channel)*

Typical @ 25

°C, VCC = 5.0 V

pF

CPD

Power Dissipation Capacitance (Per Transceiver Channel)*

40

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

VCC

GND

tf

tr

INPUT

A OR B

OUTPUT

B OR A

10%

50%

90%

10%

50%

90%

tTLH

tPLH

tPHL

tTHL

Figure 1.

OUTPUT

ENABLE

A OR B

A OR B

50%

50%

50%

90%

10%

tPZL

tPLZ

tPZH

tPHZ

VCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

VCC

GND

50%

Figure 2.

DIRECTION

TEST CIRCUITS

* Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3.

* Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4.

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 k

Ω