CS2000-CP

8

DS761F3

AC ELECTRICAL CHARACTERISTICS

PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-

cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will

6. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 15 for more information.

9. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd

order 100 Hz to 40 kHz bandpass filter.

10. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd

order 100 Hz Highpass filter.

12. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the

reference clock.

Parameters

Symbol

Conditions

Min

Typ

Max

Units

Crystal Frequency

Fundamental Mode XTAL

RefClkDiv[1:0] = 10

RefClkDiv[1:0] = 01

RefClkDiv[1:0] = 00

8

16

32

-

-

-

14

28

50

MHz

MHz

MHz

Reference Clock Input Frequency

RefClkDiv[1:0] = 10

RefClkDiv[1:0] = 01

RefClkDiv[1:0] = 00

8

16

32

-

-

-

14

28

56

MHz

MHz

MHz

Reference Clock Input Duty Cycle

45

-

55

%

Internal System Clock Frequency

814

MHz

Clock Input Frequency

50 Hz

-

30

MHz

2

10

-

-

-

-

UI

ns

Clock Skipping Timeout

(Notes 5, 6)20

-

-

ms

Clock Skipping Input Frequency

(Note 6)

50 Hz

-

80

kHz

PLL Clock Output Frequency

(Note 7)6

-

75

MHz

PLL Clock Output Duty Cycle

Measured at VD/2

45

50

55

%

Clock Output Rise Time

20% to 80% of VD

-

1.7

3.0

ns

Clock Output Fall Time

80% to 20% of VD

-

1.7

3.0

ns

Period Jitter

(Note 8)

-

70

-

ps rms

Base Band Jitter (100 Hz to 40 kHz)

(Notes 8, 9)

-

50

-

ps rms

Wide Band JItter (100 Hz Corner)

(Notes 8, 10)

-

175

-

ps rms

PLL Lock Time - CLK_IN (Note 11)tLC

-

-

100

1

200

3

UI

ms

PLL Lock Time - REF_CLK

-

1

3

ms

Output Frequency Synthesis Resolution (Note 12)ferr

High Resolution

High Multiplication

0

0

-

-

±0.5

±112

ppm

ppm