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SAA5491PS Datasheet(PDF) 8 Page - NXP Semiconductors |
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SAA5491PS Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 68 page  1997 Jul 07 8 Philips Semiconductors Preliminary specification Economy teletext and TV microcontrollers SAA5x9x family 6.2 Pin description Table 1 SDIP52 and QFP80 packages SYMBOL PIN DESCRIPTION SDIP52 QFP80 P2.0/TPWM 1 77 Port 2: 8-bit open-drain bidirectional port with alternative functions. P2.0/TPWM is the output for the 14-bit high precision PWM. P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6. P2.1/PWM0 2 78 P2.2/PWM1 3 79 P2.3/PWM2 4 80 P2.4/PWM3 5 9 P2.5/PWM4 6 8 P2.6/PWM5 7 1 P2.7/PWM6 8 2 P3.0/ADC0 9 3 Port 3: 8-bit open-drain bidirectional port with alternative functions. P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility. P3.4/PWM7 is the output for the 6-bit PWM7. P3.1/ADC1 10 5 P3.2/ADC2 11 6 P3.3/ADC3 12 7 P3.4/PWM7 30 44 P3.5 − 46 P3.6 − 48 P3.7 − 22 VSSD 13 12 Digital ground. P0.0 14 14 Port 0: 8-bit open-drain bidirectional port. P0.5 and P0.6 have 10 mA current sinking capability for direct drive of LEDs. P0.1 15 15 P0.2 16 16 P0.3 17 20 P0.4 18 21 P0.5 19 24 P0.6 20 25 P0.7 21 26 VSSA 22 27 Analog ground. CVBS0 23 28 Composite video inputs; a positive-going 1 V (peak-to-peak) input is required, connected via a 100 nF capacitor. CVBS1 24 29 BLACK 25 30 Video black level storage input: this pin should be connected to VSSA via a 100 nF capacitor. IREF 26 31 Reference current input for analog circuits, connected to VSSA via a 27 kΩ resistor. FRAME 27 36 De-interlace output synchronised with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection circuits. VSSD 28 37 Internally connected; this pin should be connected to digital ground. COR 29 38 Open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display. |
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