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SAA5296PS Datasheet(PDF) 9 Page - NXP Semiconductors |
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SAA5296PS Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 68 page  1997 Jul 07 9 Philips Semiconductors Preliminary specification Economy teletext and TV microcontrollers SAA5x9x family LRGBREF 31 39 DC input voltage to define the output HIGH level on the RGB pins. B 32 40 Pixel rate output of the BLUE colour information. G 33 41 Pixel rate output of the GREEN colour information. R 34 42 Pixel rate output of the RED colour information. VDS 35 43 Video/data switch push-pull output for dot rate fast blanking. HSYNC 36 45 Schmitt trigger input for a TTL level version of the horizontal sync pulse; the polarity of this pulse is programmable by register bit TXT1.H POLARITY. VSYNC 37 47 Schmitt trigger input for a TTL level version of the vertical sync pulse; the polarity of this pulse is programmable by register bit TXT1.V POLARITY. VDDA 38 49 +5 V analog power supply. VDDT 39 51 +5 V teletext power supply. OSCGND 40 56 Crystal oscillator ground. XTALIN 41 57 12 MHz crystal oscillator input. XTALOUT 42 58 12 MHz crystal oscillator output. RESET 43 59 If the reset input is HIGH for at least 3 machine cycles (36 oscillator periods) while the oscillator is running, the device is reset; this pin should be connected to VDDM via a 2.2 µF capacitor. VDDM 44 62 +5 V microcontroller power supply. P1.0/INT1 45 63 Port 1: 8-bit open-drain bidirectional port with alternate functions. P1.0/INT1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse. P1.1/T0 is the counter/timer 0. P1.2/INT0 is external interrupt 0. P1.3/T1 is the counter/timer 1. P1.6/SCL is the serial clock input for the I2C-bus. P1.7/SDA is the serial data port for the I2C-bus. P1.1/T0 46 64 P1.2/INT0 47 60 P1.3/INT1 48 61 P1.6/SCL 49 65 P1.7/SDA 50 66 P1.4 51 67 P1.5 52 68 REF+ − 50 Positive reference voltage for software driven ADC. REF −− 19 Negative reference voltage for software driven ADC. RD − 10 Read control signal to external Data Memory. WR − 11 Write control signal to external Data Memory. PSEN − 17 Enable signal for external Program Memory. ALE − 18 External latch enable signal; active HIGH. EA − 13 Control signal used to select external (LOW) or internal (HIGH) Program Memory. AD0 to AD7 − 69 to 76 Address lines A0 to A7 multiplexed with data lines D0 to D7. A8 to A15 − 55 to 52, 35 to 32 Address lines A8 to A15. SYMBOL PIN DESCRIPTION SDIP52 QFP80 |
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