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70T3589S200DRG Datasheet(PDF) 1 Page - Integrated Device Technology

Part # 70T3589S200DRG
Description  HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

70T3589S200DRG Datasheet(HTML) 1 Page - Integrated Device Technology

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©2014 Integrated Device Technology, Inc.
MARCH 2014
DSC 5666/11
1
Functional Block Diagram
Interrupt and Collision Detection Flags
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA), a 208-pin
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball
Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG is not supported on the 208-
pin PQFP package
Green parts available, see ordering information
HIGH-SPEED 2.5V
256/128/64K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70T3519/99/89S
REPEATR
A0R
CNTENR
ADSR
Dout0-8_R
Dout9-17_R
I/O0R - I/O35R
Din_R
ADDR_R
OER
BE3R
BE2R
BE1R
BE0R
R/
WR
CE0R
CE1R
1
0
1/0
FT/PIPER
1a 0a
1b 0b
1c 0c
1d 0d
dc
b
a
CLKR
,
Counter/
Address
Reg.
dc b a
0/1
0d 1d
0c 1c
0b 1b
0a 1a
B
W
2
R
B
W
1
R
B
W
0
R
FT/PIPER
Counter/
Address
Reg.
CNTENL
ADSL
REPEATL
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout18-26_R
Dout27-35_R
B
W
0
L
B
W
1
L
B
W
2
L
B
W
3
L
I/O0L -I/O35L
A17L(1)
A0L
Din_L
ADDR_L
OEL
5666 drw 01
BE3L
BE2L
BE1L
BE0L
R/
WL
CE0L
CE1L
256/128/64K x 36
MEMORY
ARRAY
CLKL
ab c d
FT/PIPEL
0/1
1d 0d
1c 0c 1b 0b 1a 0a
B
W
3
R
,
JTAG
TCK
TRST
TMS
TDO
TDI
1
0
1/0
0d 1d
0c 1c
0b 1b
0a 1a
ab
c
d
FT/PIPEL
1/0
1/0
INTERRUPT
COLLISION
DETECTION
LOGIC
R/
WL
CE 0 L
CE1L
R/
WR
CE0 R
CE1R
INTL
COL L
INTR
COLR
ZZ
CONTROL
LOGIC
ZZL
(2)
ZZR
(2)
A17R(1)
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
1. Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC's for the IDT70T3589.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
NOTES:


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