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709149S12PFG Datasheet(PDF) 5 Page - Integrated Device Technology |
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709149S12PFG Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 10 page  6.42 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 5 AC Electrical Characteristics Over the Operating Temperature Range— (Read and Write Cycle Timing) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The Pipelined output parameters (tCYC2, tCD2) always apply to the Left Port. The Right Port uses the Pipelined tCYC2 and tCD2 when FT/PIPEDR = VIH and the Flow- Through parameters (tCYC1, tCD1) when FT/PIPEDR = VIL. 709149S8 Com'l Only 709149S10 Com'l & Ind 709149S12 Com'l Only Unit Symbol Parameter Min. Max. Min. Max. Min. Max. tCYC1 Clock Cycle Time (Flow-Through)(3) 16 ____ 20 ____ 20 ____ ns tCYC2 Clock Cycle Time (Pipelined)(3) 13 ____ 15 ____ 16 ____ ns tCH1 Clock High Time (Flow-Through)(3) 6 ____ 7 ____ 8 ____ ns tCL1 Clock Low Time (Flow-Through)(3) 6 ____ 7 ____ 8 ____ ns tCH2 Clock High Time (Pipelined)(3) 6 ____ 6 ____ 6 ____ ns tCL2 Clock Low Time (Pipelined)(3) 6 ____ 6 ____ 6 ____ ns tCD1 Clock to Data Valid (Flow-Through)(3) ____ 12 ____ 15 ____ 20 ns tCD2 Clock to Data Valid (Pipelined)(3) ____ 8 ____ 10 ____ 12 ns tS Registered Signal Set-up Time 4 ____ 4 ____ 5 ____ ns tH Registered Signal Hold Time 1 ____ 1 ____ 1 ____ ns tDC Data Output Hold After Clock High 1 ____ 1 ____ 1 ____ ns tCKLZ Clock High to Output Low-Z(1,2) 2 ____ 2 ____ 2 ____ ns tCKHZ Clock High to Output High-Z(1,2) ____ 7 ____ 7 ____ 9ns tOE Output Enable to Output Valid ____ 8 ____ 8 ____ 10 ns tOLZ Output Enable to Output Low-Z(1,2) 0 ____ 0 ____ 0 ____ ns tOHZ Output Disable to Output High-Z(1,2) ____ 7 ____ 7 ____ 9ns tSCK Clock Enable, Disable Set-Up Time 4 ____ 4 ____ 5 ____ ns tHCK Clock Enable, Disable Hold Time 1 ____ 1 ____ 1 ____ ns tCWDD Write Port Clock High to Read Data Delay ____ 25 ____ 30 ____ 35 ns 3494 tbl 08 |
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