70V9389L7PFG8 datasheet(6/19 Pages) IDT

Part #	70V9389L7PFG8

Description	HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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6 / 19 page

6.42

6

IDT70V9389/289L

High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM

Industrial & Commercial Temperature Ranges

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

4. LB and UB are single buffered regardless of state of FT/PIPE.

5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.

6. I/O8 - I/O15 for IDT70V9289.

7. I/O0 - I/O7 for IDT70V9289.

Truth Table I—Read/Write and Enable Control(1,2,3)

Pin Names

Left Port

Right Port

Names

CE0L, CE1L

CE0R, CE1R

Chip Enables(3)

R/WL

R/WR

Read/Write Enable

OEL

OER

Output Enable

A0L - A15L

A0R - A15R

Address

I/O0L - I/O17L(1)

I/O0R - I/O17R(1)

Data Input/Output

CLKL

CLKR

Clock

UBL

UBR

Upper Byte Select(2)

LBL

LBR

Lower Byte Select(2)

ADSL

ADSR

Address Strobe Enable

CNTENL

CNTENR

Counter Enable

CNTRSTL

CNTRSTR

Counter Reset

FT/PIPEL

FT/PIPER

Flow-Through / Pipeline

VDD

Power (3.3V)

VSS

Ground (0V)

4856 tbl 01

OE

CLK

CE0(5)

CE1(5)

UB(4)

LB(4)

R/W

Upper Byte

I/O9-17(6)

Lower Byte

I/O0-8(7)

MODE

X

↑

H

X

High-Z

Deselected–Power Down

X

↑

X

L

X

High-Z

Deselected–Power Down

X

↑

L

H

X

High-Z

Both Bytes Deselected

X

↑

LH

L

DIN

High-Z

Write to Upper Byte Only

X

↑

LH

H

L

High-Z

DATAIN

Write to Lower Byte Only

X

↑

LH

L

DATAIN

Write to Both Bytes

L

↑

LH

H

DATAOUT

High-Z

Read Upper Byte Only

L

↑

LH

H

L

H

High-Z

DATAOUT

Read Lower Byte Only

L

↑

LH

L

H

DATAOUT

Read Both Bytes

H

X

L

H

L

X

High-Z

Outputs Disabled

4856 tbl 02

NOTES:

1. I/O0X - I/O15X for IDT70V9289.

2. LB and UB are single buffered regardless of state of FT/PIPE.

3. CEo and CE1 are single buffered when FT/PIPE = VIL,

CEo and CE1 are double buffered when FT/PIPE = VIH,

i.e. the signals take two cycles to deselect.

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