70V9369L12PFG8 datasheet(9/17 Pages) IDT

Part #	70V9369L12PFG8

Description	HIGH-SPEED 3.3V 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

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6.42

IDT70V9369L

High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

9

Timing Waveform of a Bank Select Pipelined Read(1,2)

tSC

tHC

CE0(B1)

ADDRESS(B1)

A0

A1

A2

A3

A4

A5

tSA

tHA

CLK

5648 drw 08

Q0

Q1

Q3

DATAOUT(B1)

tCH2

tCL2

tCYC2

(3)

ADDRESS(B2)

A0

A1

A2

A3

A4

A5

tSA

tHA

CE0(B2)

DATAOUT(B2)

Q2

Q4

tCD2

tCKHZ

tCD2

tCKLZ

tDC

tCKHZ

tCD2

tCKLZ

(3)

tSC

tHC

(3)

tCKHZ

(3)

tCKLZ

(3)

tCD2

A6

tDC

tSC

tHC

tSC

tHC

NOTES:

1. B1RepresentsBank#1;B2RepresentsBank#2.EachBankconsistsofoneIDT70V9369forthiswaveform,andaresetupfordepthexpansioninthisexample.ADDRESS(B1)=

ADDRESS(B2)inthissituation.

2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH.

3. Transitionismeasured0mVfromLoworHigh-impedancevoltagewiththeOutputTestLoad(Figure2).

4. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH.

5. OE=VILfortheRightPort,whichisbeingreadfrom.OE=VIHfortheLeftPort,whichisbeingwrittento.

6. IftCCS<maximumspecified,thendatafromrightportREADisnotvaliduntilthemaximumspecifiedfortCWDD.

IftCCS>maximumspecified,thendatafromrightportREADisnotvaliduntiltCCS+tCD1.tCWDDdoesnotapplyinthiscase.

7. AlltimingisthesameforbothLeftandRightports.Port"A"maybeeitherLeftorRightport.Port"B"istheoppositefromPort"A".

Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)

NOTES:

1. CE0, BEn, and ADS = VIL; CE1 and REPEAT = VIH.

2. OE=VILforPort"B",whichisbeingreadfrom. OE=VIHforPort"A",whichisbeingwrittento.

3. IftCO<minimumspecified,thendatafromPort"B"readisnotvaliduntilfollowingPort"B"clockcycle(ie,timefromwritetovalidreadonoppositeportwillbetCO+2tCYC2+tCD2).IftCO

>minimum,thendatafromPort"B"readisavailableonfirstPort"B"clockcycle(ie,timefromwritetovalidreadonoppositeportwillbetCO +tCYC2+tCD2).

4. AlltimingisthesameforLeftandRightports.Port"A"maybeeitherLeftorRightport.Port"B"istheoppositeofPort"A"

CLK"A"

R/

W"A

"

ADDRESS"A"

DATAIN"A"

CLK"B"

R/

W"B"

ADDRESS"B"

DATAOUT"B"

tSW

tHW

tSA

tHA

tSD

tHD

tSW

tHW

tSA

tHA

tCO(3)

tCD2

NO

MATCH

VALID

NO

MATCH

VALID

5648 drw 09

tDC

,

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