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70T3339S200BFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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70T3339S200BFG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 27 page ©2015 Integrated Device Technology, Inc. JUNE 2015 DSC-5652/8 1 HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70T3339/19/99S Functional Block Diagram – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz – Self-timedwriteallowsfastcycletime ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ Dual Cycle Deselect (DCD) for Pipelined Output Mode ◆ 2.5V (±100mV) power supply for core ◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port ◆ Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz ◆ Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine pitch Ball Grid Array (fpBGA) ◆ Supports JTAG features compliant with IEEE 1149.1 ◆ Green parts available, see ordering information Features: ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed data access – Commercial: 3.4 (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz)(max.) – Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) ◆ Selectable Pipelined or Flow-Through output mode ◆ Counter enable and repeat features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Interrupt and Collision Detection Flags ◆ Full synchronous operation on both ports – 5ns cycle time, 200MHz operation (14Gbps bandwidth) – Fast 3.4ns clock to data out – Data input, address, byte enable and control registers 1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399. 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. NOTES: Dout0-8_L B W 0 L B W 1 L Din_L OEL UBL LBL R/ WL CE0L CE1L ab FT/PIPEL 0/1 1b 0b 1a 0a 1 0 1/0 0b 1b 0a 1a ab FT/PIPEL 1/0 REPEATR A0R CNTENR ADSR Dout0-8_R Dout9-17_R I/O0R - I/O17R Din_R ADDR_R OER UBR LBR R/ WR CE0R CE1R FT/PIPER CLKR , Counter/ Address Reg. B W 1 R B W 0 R FT/PIPER Counter/ Address Reg. CNTENL ADSL REPEATL Dout9-17_L I/O0L - I/O17L A18L(1) A0L ADDR_L 5652 drw 01 512/256/128K x 18 MEMORY ARRAY CLKL , ba 0/1 0b 1b 0a 1a 1 0 1/0 1b 0b 1a 0a a b 1/0 INTERRUPT COLLISION DETECTION LOGIC INTL COL L INTR COLR R/ W L R/ WR CE 0 L CE1L CE0 R CE1R ZZ CONTROL LOGIC ZZL (2) ZZR (2) JTAG TCK TRST TMS TDO TDI A18R(1) |
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