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70V7519S133DRGI8 Datasheet(PDF) 11 Page - Integrated Device Technology

Part # 70V7519S133DRGI8
Description  HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

70V7519S133DRGI8 Datasheet(HTML) 11 Page - Integrated Device Technology

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6.42
IDT70V7519S
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT
/PIPEX = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
70V7519S200(5)
Com'l Only
70V7519S166(3,4)
Com'l
& Ind
70V7519S133(3)
Com'l
& Ind
Symbol
Parameter
Min.Max.
Min.Max.Min.
Max.
Unit
tCYC1
Clock Cycle Time (Flow-Through)(1)
15
____
20
____
25
____
ns
tCYC2
Clock Cycle Time (Pipelined)(1)
5
____
6
____
7.5
____
ns
tCH1
Clock High Time (Flow-Through)(1)
5
____
6
____
7
____
ns
tCL1
Clock Low Time (Flow-Through)(1)
5
____
6
____
7
____
ns
tCH2
Clock High Time (Pipelined)(2)
2.0
____
2.1
____
2.6
____
ns
tCL2
Clock Low Time (Pipelined)(1)
2.0
____
2.1
____
2.6
____
ns
tR
Clock Rise Time
____
1.5
____
1.5
____
1.5
ns
tF
Clock Fall Time
____
1.5
____
1.5
____
1.5
ns
tSA
Address Setup Time
1.5
____
1.7
____
1.8
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tSC
Chip Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHC
Chip Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSB
Byte Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHB
Byte Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSW
R/W Setup Time
1.5
____
1.7
____
1.8
____
ns
tHW
R/W Hold Time
0.5
____
0.5
____
0.5
____
ns
tSD
Input Data Setup Time
1.5
____
1.7
____
1.8
____
ns
tHD
Input Data Hold Time
0.5
____
0.5
____
0.5
____
ns
tSAD
ADS
Setup Time
1.5
____
1.7
____
1.8
____
ns
tHAD
ADS
Hold Time
0.5
____
0.5
____
0.5
____
ns
tSCN
CNTEN
Setup Time
1.5
____
1.7
____
1.8
____
ns
tHCN
CNTEN
Hold Time
0.5
____
0.5
____
0.5
____
ns
tSRPT
REPEAT
Setup Time
1.5
____
1.7
____
1.8
____
ns
tHRPT
REPEAT
Hold Time
0.5
____
0.5
____
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.0
____
4.0
____
4.2
ns
tOLZ
Output Enable to Output Low-Z
0.5
____
0.5
____
0.5
____
ns
tOHZ
Output Enable to Output High-Z
1
3.4
1
3.6
1
4.2
ns
tCD1
Clock to Data Valid (Flow-Through)(1)
____
10
____
12
____
15
ns
tCD2
Clock to Data Valid (Pipelined)(1)
____
3.4
____
3.6
____
4.2
ns
tDC
Data Output Hold After Clock High
1
____
1
____
1
____
ns
tCKHZ
Clock High to Output High-Z
1
3.4
1
3.6
1
4.2
ns
tCKLZ
Clock High to Output Low-Z
0.5
____
0.5
____
0.5
____
ns
Port-to-Port Delay
tCO
Clock-to-Clock Offset
5.0
____
6.0
____
7.5
____
ns
5618 tbl 11
4. 166MHz Industrial Temperature not available in BF208 package.
5. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC256 package only.


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