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70T3719MS166BBGI Datasheet(PDF) 10 Page - Integrated Device Technology |
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70T3719MS166BBGI Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 23 page  6.42 IDT70T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Commercial Temperature Range 10 AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C) NOTES: 1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = Vss (0V) for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be treated as DC signals, i.e. steady state during operation. 3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port. 4. Guaranteed by design (not production tested). 70T3509MS133 Com'l & Ind Symbol Parameter Min. Max. Unit tCYC1 Clock Cycle Time (Flow-Through)(1) 25 ____ ns tCYC2 Clock Cycle Time (Pipelined)(1) 7.5 ____ ns tCH1 Clock High Time (Flow-Through)(1) 10 ____ ns tCL1 Clock Low Time (Flow-Through)(1) 10 ____ ns tCH2 Clock High Time (Pipelined)(2) 3 ____ ns tCL2 Clock Low Time (Pipelined)(1) 3 ____ ns tSA Address Setup Time 1.8 ____ ns tHA Address Hold Time 0.5 ____ ns tSC Chip Enable Setup Time 1.8 ____ ns tHC Chip Enable Hold Time 0.5 ____ ns tSB Byte Enable Setup Time 1.8 ____ ns tHB Byte Enable Hold Time 0.5 ____ ns tSW R/W Setup Time 1.8 ____ ns tHW R/W Hold Time 0.5 ____ ns tSD Input Data Setup Time 1.8 ____ ns tHD Input Data Hold Time 0.5 ____ ns tSAD ADS Setup Time 1.8 ____ ns tHAD ADS Hold Time 0.5 ____ ns tSCN CNTEN Setup Time 1.8 ____ ns tHCN CNTEN Hold Time 0.5 ____ ns tSRPT REPEAT Setup Time 1.8 ____ ns tHRPT REPEAT Hold Time 0.5 ____ ns tOE Output Enable to Data Valid ____ 4.6 ns tOLZ(4) Output Enable to Output Low-Z 1 ____ ns tOHZ(4) Output Enable to Output High-Z 1 4.2 ns tCD1 Clock to Data Valid (Flow-Through)(1) ____ 15 ns tCD2 Clock to Data Valid (Pipelined)(1) ____ 4.2 ns tDC Data Output Hold After Clock High 1 ____ ns tCKHZ(4) Clock High to Output High-Z 1 4.2 ns tCKLZ(4) Clock High to Output Low-Z 1 ____ ns tINS Interrupt Flag Set Time ____ 7ns tINR Interrupt Flag Reset Time ____ 7ns tCOLS Collision Flag Set Time ____ 4.2 ns tCOLR Collision Flag Reset Time ____ 4.2 ns tZZSC Sleep Mode Set Cycles 2 ____ cycles tZZRC Sleep Mode Recovery Cycles 3 ____ cycles Port-to-Port Delay tCO Clock-to-Clock Offset 6 ____ ns 5682 tbl 11 |
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