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70T3719MS166BBGI8 Datasheet(PDF) 5 Page - Integrated Device Technology |
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70T3719MS166BBGI8 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 25 page  6.42 IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges 5 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = X. 3. OE and ZZ are asynchronous input signals. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. 5. For the examples shown here, BEn may correspond to any of the eight byte enable signals. Truth Table I—Read/Write and Enable Control (1,2,3,4,5) OE CLK CE0 CE1 Byte Enables R/W ZZ I/O Operation(6) MODE X H X All BE = X X L All Bytes= High-Z Deselected: Power Down X X L All BE = X X L All Bytes = High-Z Deselected: Power Down X L H All BE = H X L All Bytes = High-Z All Bytes Deselected X LH BEn = L, All other BE = H L L Byten = DIN, All other Bytes = High-Z Write to Byte X Only X LH BE4-7 = L, BE0-3 = H L L Byte4-7 = DIN, Byte0-3 = High-Z Write to Lower Bytes Only X LH BE4-7 = H, BE0-3 = L L L Byte4-7 = High-Z, Byte0-3 = DIN Write to Upper Bytes Only X LH BE0-7 = L L L Byte0-7 = DIN Write to All Bytes L LH BEn = L, All other BE = H H L Byten = DOUT, All other Bytes = High-Z Read Byte X Only L LH BE4-7 = L, BE0-3 = H HL Byte4-7 = DOUT, Byte0-3 = High-Z Read Lower Bytes Only L LH BE4-7 = H, BE0-3 = L HL Byte4-7 = High-Z, Byte0-3 = DOUT Read Upper Bytes Only L LH All BE = L H L All Bytes = DOUT Read All Bytes HX X X All BE = X X L All Bytes = High-Z Outputs Disabled XX XX All BE = X X H All Bytes = High-Z Sleep Mode 5687 tbl 03 Truth Table II—Address Counter Control (1,2) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. Address Previous Internal Address Internal Address Used CLK ADS(4) CNTEN REPEAT(4,6) I/O(3) MODE An X An LX HDI/O(n) External Address Used XAn An + 1 H L(5) HDI/O(n+1) Counter Enabled-Internal Address generation X An + 1 An + 1 HH HDI/O(n+1) Enabled Address Blocked-Counter disabled (An + 1 reused) XX An X X LDI/O(n) Counter Set to last valid ADS load 5687 tbl 04 |
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