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70T3539MS166BCGI8 Datasheet(PDF) 4 Page - Integrated Device Technology |
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70T3539MS166BCGI8 Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 26 page  6.42 IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges 4 Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (Input)(5) R/WL R/WR Read/Write Enable (Input) OEL OER Output Enable (Input) A0L - A18L A0R - A18R Address (Input) I/O0L - I/O35L I/O0R - I/O35R Data Input/Output CLKL CLKR Clock (Input) PL/FTL PL/FTR Pipeline/Flow-Through (Input) ADSL ADSR Address Strobe Enable (Input) CNTENL CNTENR Counter Enable (Input) REPEATL REPEATR Counter Repeat(3) BE0L - BE3L BE0R - BE3R Byte Enables (9-bit bytes) (Input)(5) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V)(1) (Input) OPTL OPTR Option for selecting VDDQX(1,2) (Input) ZZL ZZR Sleep Mode pin(4) (Input) VDD Power (2.5V)(1) (Input) VSS Ground (0V) (Input) TDI Test Data Input TDO Test Data Output TCK Test Logic Clock (10MHz) (Input) TMS Test Mode Select (Input) TRST Reset (Initialize TAP Controller) (Input) INTL INTR Interrupt Flag (Output) COLL COLR Collision Alert (Output) 5678 tbl 01 NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that port's I/Os and address controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. When REPEATX is asserted, the counter will reset to the last valid address loaded via ADSX. 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode. 5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the signals take two cycles to deselect. |
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