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MAX1166CEUP Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX1166CEUP Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 15 page Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface _______________________________________________________________________________________ 9 Track and Hold (T/H) In track mode, the analog signal is acquired on the inter- nal hold capacitor. In hold mode, the T/H switches open and the capacitive DAC samples the analog input. During the acquisition, the analog input (AIN) charges capacitor CDAC. The acquisition ends on the second falling edge of CS. At this instant, the T/H switches open. The retained charge on CDAC represents a sam- ple of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion time to restore node ZERO to zero within the limits of 16-bit resolution. Force CS low to put valid data on the bus at the end of the conversion. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal. Use the following formula to calculate acqui- sition time: tACQ = 11 (RS + RIN) ✕ 35pF where RIN = 800 Ω, RS = the input signal’s source impedance, and tACQ is never less than 1.1µs. A source impedance less than 1k Ω does not significantly affect the ADC’s performance. To improve the input signal bandwidth under AC condi- tions, drive AIN with a wideband buffer (>4MHz) that can drive the ADC’s input capacitance and settle quickly. Power-Down Modes Select standby mode or shutdown mode with the R/C bit during the second falling edge of CS (see the Selecting Standby or Shutdown Mode section). The MAX1165/MAX1166 automatically enter either standby mode (reference and buffer on) or shutdown (reference and buffer off) after each conversion depending on the status of R/C during the second falling edge of CS. Internal Clock The MAX1165/MAX1166 generate an internal conver- sion clock. This frees the microprocessor from the bur- den of running the SAR conversion clock. Total conversion time after entering hold mode (second falling edge of CS) to end of conversion (EOC) falling is 4.7µs (max). Applications Information Starting a Conversion CS and R/C control acquisition and conversion in the MAX1165/MAX1166 (Figure 2). The first falling edge of CS powers up the device and puts it in acquire mode if R/C is low. The convert start is ignored if R/C is high. The MAX1165/MAX1166 need at least 10ms (CREFADJ = 0.1µF, CREF = 4.7µF) for the internal refer- ence to wake up and settle before starting the conver- sion if powering up from shutdown. The ADC can wake up, from shutdown, to an unknown state. Put the ADC in a known state by completing one “dummy” conver- sion. The MAX1165/MAX1166 are in a known state, ready for actual data acquisition, after the completion of the dummy conversion. A dummy conversion con- sists of one full conversion cycle. The MAX1165 provides an alternative reset function to reset the device (see the RESET section). MAX1166 0.1 µF +5V ANALOG +5V DIGITAL 0.1 µF ANALOG INPUT AIN AVDD DVDD R/C CS EOC REF D0–D7 OR D8–D15 REFADJ HBEN AGND DGND 0.1 µF 4.7 µF µP DATA BUS HIGH BYTE LOW BYTE Figure 3. Typical Application Circuit for the MAX1166 AIN REF AGND ZERO AUTOZERO RAIL TRACK TRACK HOLD HOLD CSWITCH 3pF CAPACITIVE DAC CDAC = 32pF RIN 800 Ω Figure 4. Equivalent Input Circuit |
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