Detailed Description

Figure 2 is a functional diagram of the MAX3272/

MAX3272A, comprising a CML input buffer, power

detector and loss-of- signal indicators, gain stage, offset-

correction loop, and CML output buffer.

CML Input Buffer

The input buffer (Figure 3) provides 100

Ω input imped-

ance between IN+ and IN-. DC-coupling the inputs is

not recommended; this prevents the DC offset-correc-

tion circuitry from functioning properly.

Power Detect and

Loss-of-Signal Indicator

The MAX3272/MAX3272A are equipped with loss-of-sig-

nal (LOS) circuitry that indicates when the input signal is

the TH pin (see the Typical Operating Characteristics for

appropriate resistor selection). An averaging peak-

power detector compares the input signal amplitude

with this threshold and feeds the signal-detect informa-

tion to the LOS outputs, which are internally terminated

to 8k

Ω (Figure 4).

+3.3V, 2.5Gbps Low-Power

Limiting Amplifiers

6

_______________________________________________________________________________________

50

Ω

50

Ω

CONTROL

SQUELCH

OPEN

LEVEL

OPEN

MAX3272/

MAX3272A

Figure 1. Power-Supply Current Measurement

MAX3272/

MAX3272A

TTL

TTL

CONTROL

POWER

DETECTOR

IN+

IN-

100

Ω

POWER DETECTOR AND

LOS INDICATOR

CML

INPUT

BUFFER

CML

OUTPUT

BUFFER

OFFSET

CORRECTION

0.1

µF

LOWPASS

FILTER

LOS

SQUELCH

OUT+

OUT-

LEVEL

OUTPOL

LOS

CAZ1

CAZ2

TH

CLOS

Figure 2. Functional Diagram