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ISPL1048E-125LTI Datasheet(PDF) 2 Page - Lattice Semiconductor |
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ISPL1048E-125LTI Datasheet(HTML) 2 Page - Lattice Semiconductor |
2 / 16 page Specifications ispLSI 1048E 2 Functional Block Diagram Figure 1. ispLSI 1048E Functional Block Diagram The device also has 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered in- put, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to mini- mize overall output switching noise. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1048E device contains six Megablocks. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1048E device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Output Routing Pool (ORP) B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool (ORP) C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool (ORP) F7 F6 F5 F4 F3 F2 F1 F0 Input Bus Output Routing Pool (ORP) E7 E6 E5 E4 E3 E2 E1 E0 Input Bus A0 A1 A2 A3 A4 A5 A6 A7 Generic Logic Blocks (GLBs) Megablock Global Routing Pool (GRP) CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 Clock Distribution Network D7 D6 D5 D4 D3 D2 D1 D0 I/O 94 I/O 95 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 IN 11 I/O 78 I/O 79 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 IN 9 IN 10 I/O 17 I/O 16 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 SDO/ IN 3 Y 0 Y 1 Y 2 Y 3 I/O 33 I/O 32 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 SCLK/ IN 5 IN 4 IN 7 IN 6 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 I/O 0 I/O 1 I/O 2 I/O 3 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1 I/O 4 I/O 5 ispEN/NC RESET Input Bus Input Bus 0139F(2)-48B-isp IN 8 GOE 0 GOE 1 IN 2 |
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