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ISPL1048E-100LT Datasheet(PDF) 5 Page - Lattice Semiconductor |
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ISPL1048E-100LT Datasheet(HTML) 5 Page - Lattice Semiconductor |
5 / 16 page Specifications ispLSI 1048E 5 External Timing Parameters Over Recommended Operating Conditions tpd1 UNITS TEST COND. 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030A/1048E 1 4 3 1 tsu2 + tco1 ( ) -90 MIN. MAX. DESCRIPTION # 2 PARAMETER A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 ns tpd2 A 2 Data Propagation Delay, Worst Case Path – ns fmax (Int.) A 3 Clock Frequency with Internal Feedback 90.9 – MHz fmax (Ext.) – 4 Clock Frequency with External Feedback – MHz fmax (Tog.) – 5 Clock Frequency, Max. Toggle – MHz tsu1 – 6 GLB Reg. Setup Time before Clock,4 PT Bypass – ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – ns th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – ns tsu2 – 9 GLB Reg. Setup Time before Clock – ns tco2 – 10 GLB Reg. Clock to Output Delay – ns th2 – 11 GLB Reg. Hold Time after Clock – ns tr1 A 12 Ext. Reset Pin to Output Delay – ns trw1 – 13 Ext. Reset Pulse Duration – ns tptoeen B 14 Input to Output Enable – ns tptoedis C 15 Input to Output Disable – ns twh – 18 External Synchronous Clock Pulse Duration, High 4.0 ns twl – 19 External Synchronous Clock Pulse Duration, Low 4.0 ns tsu3 – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) – ns th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – ns 71.0 125.0 6.5 0.0 7.5 0.0 6.5 4.0 0.0 12.5 6.5 7.5 13.5 15.0 15.0 – – ( ) 1 twh + twl tgoeen B 16 Global OE Output Enable – ns 9.0 tgoedis C 17 Global OE Output Disable – ns -125 MIN. MAX. – 7.5 – 125.0 – – – – – 0.0 6.5 – 0.0 – 5.0 – – 3.0 3.0 3.0 – 0.0 – 91.0 167.0 5.5 4.5 – – 5.5 – 10.0 – 12.0 12.0 – – 10.0 – 7.0 – 7.0 9.0 -100 MIN. MAX. – 10.0 – 100.0 – – – – – – – – – – – – – 4.0 4.0 – – 71.0 125.0 6.5 0.0 7.5 0.0 6.5 3.5 0.0 12.5 6.5 7.5 13.5 15.0 15.0 – – – 9.0 – 9.0 |
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