6

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

MARCH 2013

SIGNAL DESCRIPTIONS:

INPUTS:

Data inputs for 18-bit wide data.

CONTROLS:

RESET (RS)

ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate.

During reset, both internal read and write pointers are set to the first location.

Aresetisrequiredafterpower-upbeforeawriteoperationcantakeplace.The

FullFlag(FF),Half-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)

registerisinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefault

values.

WRITE CLOCK (WCLK)

AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock

(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH

transitionofWCLK.

The Write and Read Clocks can be asynchronous or coincident.

WRITE ENABLE (WEN)

WhentheWENinput isLOWandLDinputisHIGH,datamaybeloadedinto

the FIFO RAM array on the rising edge of every WCLK cycle if the device is

notfull. DataisstoredintheRAMarraysequentiallyandindependentlyofany

ongoing read operation.

WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK

cycle.

Topreventdataoverflow,FFwillgoLOW,inhibitingfurtherwriteoperations.

Upon the completion of a valid read cycle, FF will go HIGH allowing a write to

occur. The FF flag is updated on the rising edge of WCLK. WEN is ignored

when the FIFO is full.

READ CLOCK (RCLK)

DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead

Clock (RCLK), when Output Enable (OE) is set LOW.

The Write and Read Clocks can be asynchronous or coincident.

READ ENABLE (REN)

WhenReadEnableisLOWand LDinputisHIGH,dataisloadedfromthe

RAM array into the output register on the rising edge of every RCLK cycle if

the device is not empty.

WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand

the previous data value.

FIFO,mustberequestedusingREN. Whenthelastwordhasbeenreadfrom

theFIFO,theEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations.

REN is ignored when the FIFO is empty. Once a write is performed, EF will

go HIGH allowing a read to occur. The EF flag is updated on the rising edge

of RCLK.

OUTPUT ENABLE (OE)

When Output Enable (OE) is enabled (LOW), the parallel output buffers

receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput

databusisinahigh-impedancestate.

LOAD (LD)

The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices con-

tain two 12-bit offset registers with data on the inputs, or read on the outputs.

When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs

D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH

transition of the Write Clock (WCLK). When the LD pin and (WEN) are held

LOWthendataiswrittenintotheFullOffsetregisteronthesecondLOW-to-HIGH

transitionof(WCLK).Thethirdtransitionofthewriteclock(WCLK)againwrites

totheEmptyOffsetregister.

However,writingalloffsetregistersdoesnothavetooccuratonetime.One

ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the

FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,

and WEN is LOW, the next offset register in sequence is written.

EMPTY OFFSET REGISTER

17

11

0

001FH (72205) 003FH (72215):

007FH (72225/72235/72245)

FULL OFFSET REGISTER

17

11

0

DEFAULT VALUE

DEFAULT VALUE

001FH (72205) 003FH (72215):

007FH (72225/72235/72245)

2766 drw 05

Figure 2. Write Offset Register

NOTE:

1. The same selection sequence applies to reading from the registers. REN is enabled and

read is performed on the LOW-to-HIGH transition of RCLK.

Figure 3. Offset Register Location and Default Values

NOTE:

1. Any bits of the offset register not being programmed should be set to zero.

LD

WEN

WCLK

Selection

0

0

Writingtooffsetregisters:

EmptyOffset

FullOffset

0

1

NoOperation

1

0

Write Into FIFO

1

1

NoOperation