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72235LB10JG8 Datasheet(PDF) 11 Page - Integrated Device Technology |
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72235LB10JG8 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 16 page 11 IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES MARCH 2013 NOTE: 1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). Figure 9. Empty Flag Timing Figure 10. Write Programmable Registers WCLK D0 - D17 RCLK Q0 - Q17 tDS tENS tA tSKEW2 DATA WRITE 1 DATA READ tENH tREF tDS tENS DATA WRITE 2 tENH tREF DATA IN OUTPUT REGISTER tFRL (1) LOW 2766 drw 11 tREF tSKEW2 tFRL (1) WCLK tCLKH tCLKL tCLK tENS tENH LD WEN D0–D15 tDS tDH PAE OFFSET PAF OFFSET D0–D11 PAE OFFSET tENS 2766 drw 12 Figure 11. Read Programmable Registers RCLK tCLKH tCLKL tCLK tENS tENH Q0–Q15 PAE OFFSET PAF OFFSET PAE OFFSET UNKNOWN tA tENS 2766 drw 13 |
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