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HY29F400TR45 Datasheet(PDF) 7 Page - Hynix Semiconductor |
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HY29F400TR45 Datasheet(HTML) 7 Page - Hynix Semiconductor |
7 / 40 page 7 Rev. 5.2/May 01 HY29F400 Table 3. HY29F400 Bus Operations Requiring High Voltage 1, 2 Notes: 1. L = V IL, H = VIH, X = Don’t Care. See DC Characteristics for voltage levels. 2. Address bits not specified are Don’t Care. 3. See text for additional information. 4. SA = sector address. See Table 1. 5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L). The ‘Device Commands’ section of this document provides details on the specific device commands implemented in the HY29F400. Output Disable Operation When the OE# input is at V IH, output data from the device is disabled and the data bus pins are placed in the high impedance state. Standby Operation When the system is not reading from or writing to the HY29F400, it can place the device in the Standby mode. In this mode, current consump- tion is greatly reduced, and the data bus outputs are placed in the high impedance state, indepen- dent of the OE# input. The Standby mode can be invoked using two methods. The device enters the CE# CMOS Standby mode if the CE# and RESET# pins are both held at V CC ± 0.5V. Note that this is a more restricted voltage range than V IH. If both CE# and RESET# are held High, but not within V CC ± 0.5V, the device will be in the CE# TTL Standby mode, but the standby current will be greater. The device enters the RESET# CMOS Standby mode when the RESET# pin is held at V SS ± 0.5V. If RESET# is held Low but not within V SS ± 0.5V, the HY29F400 will be in the RESET# TTL Standby mode, but the standby current will be greater. See Hardware Reset Operation section for additional information on the reset operation. The device requires standard access time (t CE) for read access when the device is in either of the standby modes, before it is ready to read data. If the device is deselected during erasure or pro- gramming, it continues to draw active current until the operation is completed. Hardware Reset Operation The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven Low for the minimum specified period, the device immediately termi- nates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. If an operation was interrupted by the as- sertion of RESET#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. Current is reduced for the duration of the RESET# pulse as described in the Standby Operation sec- tion above. n o i t a r e p O 3 # E C # E O # E W # T E S E R ] 2 1 : 7 1 [ A ] 9 [ A ] 6 [ A ] 1 [ A ] 0 [ A ] 0 : 7 [ Q D ] 8 : 5 1 [ Q D # E T Y B H = # E T Y B L = 5 t c e t o r P r o t c e SL V D I XH A S 4 V D I XXX X X Z - h g i H t c e t o r p n U r o t c e SV D I V D I XH X V D I XXX X X Z - h g i H r o t c e S y r a r o p m e T t c e t o r p n U XXX V D I X XXXX D N I D N I Z - h g i H e d o C r e r u t c a f u n a ML L H H X V D I LLL D A x 0X Z - h g i H e c i v e D e d o C B 0 0 4 F 9 2 Y H LL H H X V D I LL H B A x 0 2 2 x 0Z - h g i H T 0 0 4 F 9 2 Y H 3 2 x 0 p u o r G r o t c e S n o i t c e t o r P n o i t a c i f i r e V LL H H A S 4 V D I LH L = 0 0 x 0 d e t c e t o r p n U XZ - h g i H = 1 0 x 0 d e t c e t o r P |
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