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71321SA55JGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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71321SA55JGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 17 page  ©2008 Integrated Device Technology, Inc. OCTOBER 2008 DSC-2691/13 1 HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS IDT71321SA/LA IDT71421SA/LA Features ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 20/25/35/55ns (max.) – Industrial: 25/55ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT71321/IDT71421SA — Active: 325mW (typ.) — Standby: 5mW (typ.) – IDT71321/421LA — Active: 325mW (typ.) — Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ Two INT flags for port-to-port communications Functional Block Diagram NOTES: 1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270 Ω. IDT71421 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270 Ω. ◆ ◆ ◆ ◆ ◆ MASTER IDT71321 easily expands data bus width to 16-or- more-bits using SLAVE IDT71421 ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic (IDT71321 only) ◆ ◆ ◆ ◆ ◆ BUSY output flag on IDT71321; BUSY input on IDT71421 ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ Battery backup operation – 2V data retention (LA only) ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 5V ±10% power supply ◆ ◆ ◆ ◆ ◆ Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information I/O Control Address Decoder MEMORY ARRAY ARBITRATION and INTERRUPT LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A10L A0L 2691 drw 01 I/O0L-I/O7L CEL OEL R/ WL INTL BUSYR I/O0R-I/O7R A10R A0R INTR CER OER (2) (1,2) (1,2) (2) R/ WR CER OER R/ WR 11 11 |
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