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71321SA35PFGI Datasheet(PDF) 9 Page - Integrated Device Technology

Part # 71321SA35PFGI
Description  HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

71321SA35PFGI Datasheet(HTML) 9 Page - Integrated Device Technology

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6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the
Operating Temeprature and Supply Voltage Range(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, tWC = tBAA + tWP, since R/
W = VIL must occur after tBAA .
3. If
OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If
OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
4. 'X' in part numbers indicates power rating (SA or LA).
Symbol
Parameter
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Unit
Min.
Max.
Min.
Max.
WRITE CYCLE
tWC
Write Cycle Time(2)
20
____
25
____
ns
tEW
Chip Enable to End-of-Write
15
____
20
____
ns
tAW
Address Valid to End-of-Write
15
____
20
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
tWP
Write Pulse Width(3)
15
____
15
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
12
____
ns
tHZ
Output High-Z Time(1)
____
10
____
10
ns
tDH
Data Hold Time
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z
(1)
____
10
____
10
ns
tOW
Output Active from End-of-Write(1)
0
____
0
____
ns
2691 tbl 09a
Symbol
Parameter
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Unit
Min.
Max.
Min.
Max.
WRITE CYCLE
tWC
Write Cycle Time(2)
35
____
55
____
ns
tEW
Chip Enable to End-of-Write
30
____
40
____
ns
tAW
Address Valid to End-of-Write
30
____
40
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
tWP
Write Pulse Width(3)
25
____
30
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
20
____
ns
tHZ
Output High-Z Time(1)
____
15
____
25
ns
tDH
Data Hold Time
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z(1)
____
15
____
30
ns
tOW
Output Active from End-of-Write(1)
0
____
0
____
ns
2691 tbl 09b


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